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ADCMP567 Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción
Fabricante
ADCMP567
ADI
Analog Devices ADI
ADCMP567 Datasheet PDF : 14 Pages
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ADCMP567
TIMING INFORMATION
LATCH ENABLE
LATCH ENABLE
tS
tPL
tH
Data Sheet
50%
DIFFERENTIAL
VIN
INPUT VOLTAGE
VOD
VREF ± VOS
Q OUTPUT
tPDL
tPLOH
50%
tPDH
tF
Q OUTPUT
tPLOL
tR
Figure 3. System Timing Diagram
50%
03633-0-003
The timing diagram in Figure 3 shows the ADCMP567 compare and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing
tPDH
Input to output high
delay
tPDL
Input to output low
delay
tPLOH
Latch enable to output
high delay
tPLOL
Latch enable to output
low delay
tH
Minimum hold time
tPL
Minimum latch enable
pulse width
tS
Minimum setup time
tR
Output rise time
tF
Output fall time
VOD
Voltage overdrive
Description
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output low-to-high transition
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output high-to-low transition
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output low-to-high transition
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output high-to-low transition
Minimum time after the negative transition of the Latch Enable signal that the input signal must
remain unchanged to be acquired and held at the outputs
Minimum time that the Latch Enable signal must be high to acquire an input signal change
Minimum time before the negative transition of the Latch Enable signal that an input signal change
must be present to be acquired and held at the outputs
Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points
Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points
Difference between the differential input and reference input voltages
Rev. A | Page 8 of 14

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