ADC101S051 Ver la hoja de datos (PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
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ADC101S051
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
ADC101S051 Datasheet PDF : 16 Pages
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ADC101S051 Converter Electrical Characteristics (Notes 7, 9) (Continued)
The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps,
CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 9)
Units
AC ELECTRICAL CHARACTERISTICS
DC
SCLK Duty Cycle
fSCLK = 10 MHz
40
% (min)
50
60
% (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Acquisition Time + Conversion Time
400
ns (max)
20
SCLK cycles
tQUIET
tAD
tAJ
(Note 10)
Aperture Delay
Aperture Jitter
50
ns (min)
3
ns
30
ps
ADC101S051 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz, CL = 25 pF,
fSAMPLE = 200 ksps to 500 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
tCS
Minimum CS Pulse Width
10
tSU
CS to SCLK Setup Time
10
Delay from CS Until SDATA TRI-STATE®
tEN
Disabled (Note 11)
20
tACC
tCL
tCH
tH
Data Access Time after SCLK Falling Edge
(Note 12)
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High
tDIS
Impedance (Note 13)
VA = +2.7V to +3.6V
VA = +4.75V to +5.25V
VA = +2.7V to +3.6V
VA = +4.75V to +5.25V
VA = +2.7V to +3.6V
VA = +4.75V to +5.25V
40
20
0.4 x tSCLK
0.4 x tSCLK
7
5
25
5
25
5
tPOWER-UP Power-Up Time from Full Power-Down
1
Units
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax − TA) / θJA. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion.
Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.
Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
Note 13: tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted
to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading.
5
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