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ADC1003S030 Datasheet PDF : 19 Pages
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Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Table 6. Characteristics …continued
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Rlad
TCRlad
ladder resistance
ladder resistor
temperature coefficient
-
245
-
-
456
-
m/K
Voffset
offset voltage
BOTTOM
TOP
[2] -
175
-
mV
[2] -
175
-
mV
Vi(a)(p-p)
peak-to-peak analog input
voltage
[3] 1.90
1.95
2.00
V
Digital outputs D9 to D0 and IR (Referenced to OGND)
VOL
LOW-level output voltage IOL = 1 mA
VOH
HIGH-level output voltage IOH = 1 mA
IOZ
OFF-state output current 0.5 V < VO < VCCO
Switching characteristics; clock input CLK see Figure 4;[1]
0
-
VCCO 0.5 -
20
-
0.5
V
VCCO
V
+20
A
fclk(max)
maximum clock frequency ADC1003S030TS
30
-
-
MHz
ADC1003S040TS
40
-
-
MHz
ADC1003S050TS
50
-
-
MHz
tw(clk)H
HIGH clock pulse width
full effective
bandwidth
8.5
-
-
ns
tw(clk)L
LOW clock pulse width
full effective
bandwidth
5.5
-
-
ns
Analog signal processing
Linearity
INL
integral non-linearity
fclk = 40 MHz;
ramp input
-
0.8
2.0
LSB
DNL
differential non-linearity
fclk = 40 MHz;
ramp input
-
0.5
0.9
LSB
Eoffset
EG
offset error
gain error
middle code
-
1
-
LSB
from device to device, [4] -
3
-
%
using internal
reference voltage
Bandwidth (fclk = 40 MHz)
B
bandwidth
full-scale sine wave
[5] -
15
-
MHz
75 % full-scale sine
[5] -
wave
20
-
MHz
small signal at
[5] -
mid-scale;
VI = 10 LSB at
code 512
350
-
MHz
ts(LH)
LOW to HIGH settling time full-scale square
[6] -
wave; see Figure 6
1.5
3.0
ns
ts(HL)
HIGH to LOW settling time full-scale square
[6] -
wave; see Figure 6
1.5
3.0
ns
ADC1003S030_040_050_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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