AD9963BCPZ Ver la hoja de datos (PDF) - Analog Devices
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AD9963BCPZ Datasheet PDF : 61 Pages
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Data Sheet
AD9961/AD9963
AUX33V 1
AUXADCREF 2
RXQP 3
RXQN 4
RXGND 5
RXBIAS 6
RX18V 7
RX33V 8
RX18VF 9
RXCML 10
RXGND 11
RXIN 12
RXIP 13
LDO_EN 14
RESET 15
SCLK 16
CS 17
SDIO 18
PIN 1
INDICATOR
AD9963
(TOP VIEW)
54 DLLFILT
53 DLL18V
52 DVDD18
51 DRVDD
50 TXD0
49 TXD1
48 TXD2
47 TXD3
46 TXD4
45 TXD5
44 TXD6
43 TXD7
42 TXD8
41 TXD9
40 TXD10
39 TXD11
38 TXIQ/TXnRX
37 TXCLK
NOTES
1. EXPOSED PAD MUST BE SOLDERED TO PCB.
Figure 3. AD9963 Pin Configuration
Table 9. AD9963 Pin Function Descriptions
Pin No. Mnemonic
Description
1
AUX33V
Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 10%, 1.8 V ± 10% If Auxiliary ADC Is
Powered Down).
2
AUXADCREF
Reference Output (or input) for Auxiliary ADC.
3, 4
RXQP, RXQN
Differential ADC Q Inputs. Full-scale input voltage range is 1.56 V p-p differential.
5, 11
RXGND
Receive Path Ground.
6
RXBIAS
External Bias Resistor Connection. This voltage is nominally 0.5 V. A 10 kΩ resistor can be connected
between this pin and analog ground to improve the Rx ADC full-scale accuracy.
7
RX18V
Output of RX18V Voltage Regulator.
8
RX33V
Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to
Pin 7.
9
RX18VF
Output of RX18VF Voltage Regulator.
10
RXCML
ADC Common-Mode Voltage Output.
12, 13
RXIN, RXIP
Differential ADC I Inputs. Full-scale input voltage range is 1.56 V p-p differential.
14
LDO_EN
Control pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All
LDOs).
15
RESET
Reset. Active low to reset the configuration registers to default values and reset device.
16
SCLK
Clock Input for Serial Port.
17
CS
Active Low Chip Select.
18
SDIO
Bidirectional Data Line for Serial Port.
19, 34
DGND
Digital Core Ground.
20, 33, 51 DRVDD
Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V).
21 to 32 TRXD11 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode.
35
TRXIQ
Output Signal Indicating from Which ADC the Output Data Is Sourced.
36
TRXCLK
Qualifying Clock for the TRXD Bus.
37
TXCLK
Qualifying Clock for the TXD Bus. It can be configured as either an input or output.
38
TXIQ/TXnRX
Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full-
duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC Input Data is intended.
39 to 50 TXD11 to TXD0
TxDAC Input Data.
52
DVDD18
Digital Core 1.8 V Supply.
53
DLL18V
Output of DLL18V Voltage Regulator.
Rev. A | Page 11 of 60
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