AD9925 Ver la hoja de datos (PDF) - Analog Devices

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AD9925

CCD Signal Processor with Vertical Driver and Precision Timing ™ Generator

Analog Devices 

AD9925

CCD

SIGNAL

3

4

1

2

RG

5

6

H1

H2

7

8

H3

H4

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE.

2. RG FALLING EDGE.

3. SHP SAMPLE LOCATION.

4. SHD SAMPLE LOCATION.

5. H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

7. H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).

Figure 18. High Speed Clock Programmable Locations

Figure 20 shows the default timing locations for all of the high

speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9925

features on-chip output drivers for the RG and H1 to H4 out-

puts. These drivers are powerful enough to directly drive the

CCD inputs. The H-driver and RG current can be adjusted for

optimum rise/fall time with a particular load by using the

DRVCONTROL register (Addr x35). The 3-bit drive setting for

each output is adjustable in 4.1 mA increments, with the mini-

mum setting of 0 equal to OFF or three-state and the maximum

setting of 7 equal to 30.1 mA.

As shown in Figure 18, Figure 19, and Figure 20, the H2 and H4

outputs are inverses of H1 and H3, respectively. The H1/H2

crossover voltage is approximately 50% of the output swing. The

crossover voltage is not programmable.

Digital Data Outputs

The AD9925 data output and DCLK phase are programmable

using the DOUTPHASE register (Addr x37, Bits [5:0]). Any

edge from 0 to 47 may be programmed, as shown in Figure 21.

Normally, the DOUT and DCLK signals will track in phase,

based on the DOUTPHASE register contents. The DCLK out-

put phase can also be held fixed with respect to the data outputs

by changing the DCLKMODE register high (Addr x37, Bit [6]).

In this mode, the DCLK output will remain at a fixed phase

equal to CLO (the inverse of CLI), while the data output phase

is still programmable.

There is a fixed output delay from the DCLK rising edge to the

DOUT transition, called tOD. This delay can be programmed to

four values between 0 ns and 12 ns by using the DOUTDELAY

register (Addr x37, Bits [8:7]). The default value is 8 ns.

The pipeline delay through the AD9925 is shown in Figure 22.

After the CCD input is sampled by SHD, there is an 11 cycle

delay until the data is available.

Table 8. Timing Core Register Parameters for H1, H3, RG, SHP/SHD

Parameter

Length

Range

Description

Polarity

1b

High/Low

Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)

Positive Edge

6b

0 to 47 Edge Location

Positive Edge Location for H1, H3, and RG

Negative Edge

6b

0 to 47 Edge Location

Negative Edge Location for H1, H3, and RG

Sampling Location 6 b

0 to 47 Edge Location

Sampling Location for Internal SHP and SHD Signals

Drive Strength

3b

0 to 47 Current Steps

Drive Current for H1 to H4 and RG Outputs (4.1 mA per Step)

Rev. A | Page 16 of 96

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