AD9925 Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

AD9925

CCD Signal Processor with Vertical Driver and Precision Timing ™ Generator

Analog Devices 

HBLK

H1/H3

H2/H4

TOG1

TOG2 TOG3

TOG4 TOG5

TOG6

AD9925

SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS

Figure 26. Generating Special HBLK Patterns

Increasing H-Clock Width during HBLK

The AD9925 will also allow the H1 to H4 pulse width to be

increased during the HBLK interval. The H-clock pulse width

can increase by reducing the H-clock frequency (see Figure 27).

The HBLKWIDTH register, at Bank 1 Address 0x38, is a 3-bit

register that allows the H-clock frequency to be reduced by 1/2,

1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency will

only occur for H1 to H4 pulses that are located within the

HBLK area.

Table 12. HBLK Width Register

Register

Length Range

HBLKWIDTH 3 b

1 to 1/14

Description

Controls H1 to H4 width

during HBLK as a frac-

tion of pixel rate

0: same frequency as

pixel rate

1: 1/2 pixel frequency,

i.e., doubles the H1 to H4

pulse width

2: 1/4 pixel frequency

3: 1/6 pixel frequency

4: 1/8 pixel frequency

5: 1/10 pixel frequency

6: 1/12 pixel frequency

7: 1/14 pixel frequency

HORIZONTAL TIMING SEQUENCE EXAMPLE

Figure 28 shows an example CCD layout. The horizontal register

contains 28 dummy pixels, which will occur on each line clocked

from the CCD. In the vertical direction, there are 10 optical black

(OB) lines at the front of the readout and 2 at the back of the

readout. The horizontal direction has 4 OB pixels in the front

and 48 in the back.

Figure 29 shows the basic sequence layout to be used during the

effective pixel readout. The 48 OB pixels at the end of each line

are used for the CLPOB signals. PBLK is optional and is often

used to blank the digital outputs during the noneffective CCD

pixels. HBLK is used during the vertical shift interval. The

HBLK, CLPOB, and PBLK parameters are programmed in the

vertical sequence registers.

More elaborate clamping schemes may be used, such as adding

in a separate sequence to clamp during the entire shield OB

lines. This requires configuring a separate vertical sequence for

reading out the OB lines.

HBLK

H1/H3

H2/H4

1/FPIX

2 × (1/FPIX)

H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS

SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, OR 1/14 USING HBLKWIDTH REGISTER

Figure 27. Generating Wide H-Clock Pulses during HBLK Interval

Rev. A | Page 21 of 96

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