AD9914 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9914

3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

Analog Devices 

Data Sheet

AD9914

AC SPECIFICATIONS

AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT =

20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

Table 2.

Parameter

REF CLK INPUT

REF CLK Multiplier Bypassed

Input Frequency Range

Duty Cycle

Minimum Differential Input Level

System Clock (SYSCLK) PLL Enabled

VCO Frequency Range

VCO Gain (KV)

Maximum PFD Rate

CLOCK DRIVERS

SYNC_CLK Output Driver

Frequency Range

Duty Cycle

Rise Time/Fall Time (20% to 80%)

SYNC_OUT Output Driver

Frequency Range

Duty Cycle

Rise Time (20% to 80%)

Fall Time (20% to 80%)

DAC OUTPUT CHARACTERISTICS

Output Frequency Range (1st Nyquist

Zone)

Output Resistance

Min

500

45

632

2400

45

33

0

Output Capacitance

Full-Scale Output Current

Gain Error

Output Offset

Voltage Compliance Range

Wideband SFDR

−10

AVDD −

0.50

101.1 MHz Output

427.5 MHz Output

696.5 MHz Output

1396.5 MHz Output

Narrow-Band SFDR

100.5 MHz Output

427.5 MHz Output

696.5 MHz Output

1396.5 MHz Output

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power-Down

Time Required to Leave Power-Down

Minimum Master Reset time

24

Maximum DAC Calibration Time (tCAL)

Maximum PLL Calibration Time (tREF_CLK)

Maximum Profile Toggle Rate

Typ Max

Unit

3500

55

2500

60

125

MHz

%

mV p-p

MHz

MHz/V

MHz

Test Conditions/Comments

Input frequency range

Maximum fOUT is 0.4 × fSYSCLK

Equivalent to 316 mV swing on each leg

146

MHz

50 55

%

650

ps

9.1

MHz

66

%

1350

ps

1670

ps

10 pF load

CFR2 register, Bit 9 = 1

10 pF load

10 pF load

1750

MHz

50

Ω

1

pF

20.48

mA

+10

% FS

0.6

μA

AVDD + V

0.50

−66

dBc

−65

dBc

−57

dBc

−52

dBc

−95

dBc

−95

dBc

−95

dBc

−92

dBc

Single-ended (each pin internally terminated to

AVDD (3.3V))

Range depends on DAC RSET resistor

See the Typical Performance Characteristics

section

0 MHz to 1750 MHz

0 MHz to 1750 MHz

0 MHz to 1750 MHz

0 MHz to 1750 MHz

See the Typical Performance Characteristics

section

±500 kHz

±500 kHz

±500 kHz

±500 kHz

45

250

152

ns

ns

SYSCLK cycles

µs

Power-down mode loses DAC/PLL calibration

settings

Must recalibrate DAC/PLL

fCAL = fSYSCLK/384 USR0 register, Bit 6 = 0; see the

DAC Calibration Output section for formula

16

ms

8

ms

PFD rate = 25 MHz

PFD rate = 50 MHz

2

SYNC_CLK period

Rev. C | Page 5 of 48

Share Link: