AD9889 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD9889 Datasheet PDF : 48 Pages
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Pin Type
POWER SUPPLY
CONTROL
Pin No.
24, 29, 36, 41
1, 61, 62, 63, 64
16, 19, 20, 21
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79,
80
47
46
48
49
45
44
Mnemonic
AVDD
DVDD
PVDD
GND
SDA
SCL
MDA
MCL
DDSDA
DDCSCL
Description
Output Power Supply
Digital and I/O Power Supply
PLL Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock (100 kHz Maximum)
Serial Port Data I/O to HDCP Keys
Serial Port Data Clock to HDCP Keys
Serial Port Data I/O to Receiver
Serial Port Data Clock to Receiver
AD9889
Value
1.8 V
1.8 V
1.8 V
0V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Table 5. Pin Function Descriptions
Pin Mnemonic
Description
OUTPUTS
TxC+
Differential Clock Output at Pixel Clock Rate; Transition Minimized Differential Signaling (TMDS).
TxC−
Differential Clock Output Complement.
Tx2+
Differential Output of the Red Data at 10× the Pixel Clock Rate; TMDS.
Tx2−
Differential Red Output Complement.
Tx1+
Differential Output of the Green Data at 10× the Pixel Clock Rate; TMDS.
Tx1−
Differential Green Output Complement.
Tx0+
Differential Output of the Blue Data at 10× the Pixel Clock Rate; TMDS.
Tx0−
Differential Blue Output Complement.
INT
Monitor Sense.
SERIAL PORT (2-WIRE)
SDA
Serial Port Data I/O.
SCL
Serial Port Data Clock.
DDSDA
Serial Port Data I/O Master to Receiver.
DDCSCL
Serial Port Data Clock Master to Receiver.
MDA
Serial Port Data I/O Master to HDCP Keys.
MCL
Serial Port Data Clock Master to HDCP Keys.
For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.
INPUTS
D[23:0]
Digital Input in RGB or YCbCr Format.
CLK
Video Clock Input.
DE
Data Enable for Video Data.
HSYNC
Horizontal Sync Input.
VSYNC
Vertical Sync Input. This is the input for vertical sync.
EXT_SW
Swing Adjust Sets the Differential Output Voltage or Swing. An 887 Ω resistor (1% tolerance) should be placed
between this pin and ground.
HPD
Hot Plug Detect. This indicates to the interface whether the receiver is connected.
S/PDIF
S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface.
MCLK
Audio Reference Clock. Set either to 128 × fs or 256 × fs.
I2S[3:0]
I2S Audio Inputs. These represent the eight channels of audio (two per input) available through I2S.
I2S CLK
I2S Audio Clock.
LRCLK
Left/Right Channel Selection.
PD/A0
Power Down.
Rev. 0 | Page 7 of 48
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