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AD9674

Octal Ultrasound Analog Front End

Analog Devices 

AD9674

Data Sheet

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, and

digital HPF bypassed, unless otherwise noted.

Table 3.

Parameter1

CLOCK2

Clock Rate

40 MSPS (Mode I)

65 MSPS (Mode II)

80 MSPS (Mode III)3

125 MSPS (Mode IV)4

Clock Pulse Width High (tEH)

Clock Pulse Width Low (tEL)

OUTPUT PARAMETERS2, 5

Propagation Delay (tPD)

Rise Time (tR) (20% to 80%)

Fall Time (tF) (20% to 80%)

DCO± Period (tDCO)6

FCO± Propagation Delay (tFCO)

DCO± Propagation Delay (tCPD)7

DCO± to Data Delay (tDATA)7

DCO± to FCO± Delay (tFRAME)7

Data to Data Skew (tDATA-MAX − tDATA-MIN)

TX_TRIG± to CLK± Setup Time (tSETUP)

TX_TRIG± to CLK± Hold Time (tHOLD)

Wake-Up Time (Standby)

Wake-Up Time (Power-Down)

ADC Pipeline Latency

APERTURE

Aperture Uncertainty (Jitter), tA

LO GENERATION

MLO± Frequency

4LO Mode

8LO Mode

16LO Mode

RESET± to MLO± Setup Time (tSETUP)

RESET± to MLO± Hold Time (tHOLD)

Temperature Min

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

25°C

25°C

25°C

25°C

Full

25°C

20.5

20.5

20.5

20.5

10.8 − 1.5 × tDCO

10.8 − 1.5 × tDCO

(tSAMPLE/28) − 300

(tSAMPLE/28) − 300

1

1

Full

4

Full

8

Full

16

Full

1

Full

1

Typ

3.75

3.75

10.8

300

300

tSAMPLE/7

10.8

tFCO + (tSAMPLE/28)

tSAMPLE/28

tSAMPLE/28

±225

2

375

16

<1

tMLO/2

tMLO/2

Max

Unit

40

MHz

65

MHz

80

MHz

125

MHz

ns

ns

10.8 + 1.5 × tDCO

10.8 + 1.5 × tDCO

(tSAMPLE/28) + 300

(tSAMPLE/28) + 300

±400

ns

ps

ps

ns

ns

ns

ps

ps

ps

ns

ns

µs

µs

Clock cycles

ps rms

40

MHz

80

MHz

160

MHz

ns

ns

1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.

2 The clock can be adjusted via the SPI.

3 Mode III must have the RF decimator enabled, unless DVDD runs at 1.8 V and 12-bit mode is configured.

4 Mode IV must have the RF decimator enabled.

5 Measurements were made using the device soldered to FR-4 material.

6 tSAMPLE/7 is based on the number of bits (14) divided by 2 because the interface uses DDR sampling.

7 tSAMPLE/28 is based on the number of bits (14) multiplied by 2 because the delays are based on half duty cycles.

Rev. A | Page 8 of 47

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