AD9520-5 Ver la hoja de datos (PDF) - Analog Devices
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AD9520-5 Datasheet PDF : 74 Pages
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AD9520-5
Data Sheet
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector2
500 kHz PFD Frequency
1 MHz PFD Frequency
10 MHz PFD Frequency
50 MHz PFD Frequency
PLL Figure of Merit (FOM)
PLL DIGITAL LOCK DETECT WINDOW3
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)3
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Min Typ Max
560 1060 1310
−320 +50 +240
Unit
ps
ps
Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
When N delay and R delay are bypassed
When N delay setting = 110b, and R delay is bypassed
−165
−162
−152
−144
−222
3.5
7.5
3.5
7
15
11
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output
of the VCO and subtracting 20 log(N) (where N is
the value of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is
an approximation of the PFD/CP in-band phase
noise (in the flat region) inside the PLL loop
bandwidth; when running closed-loop, the phase
noise, as observed at the VCO output, is increased
by 20 log(N); PLL figure of merit decreases with
decreasing slew rate; see Figure 11
Signal available at the LD, STATUS, and REFMON
pins when selected by appropriate register
settings; the lock detect threshold varies linearly
with the value of the CPRSET resistor
Selected by Register 0x017[1:0] and Register
0x018[4] (this is the threshold to go from unlock to
lock)
Register 0x017[1:0] = 00b, 01b,11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Selected by Register 0x017[1:0] and Register
0x018[4] (this is the threshold to go from lock to
unlock)
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 In-band means within the LBW of the PLL.
3 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. B | Page 6 of 74
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