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AD9520-5 Datasheet PDF : 74 Pages
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AD9520-5
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum
and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
POWER PINS
VS
VS_DRV
VCP
CURRENT SET RESISTORS
RSET Pin Resistor
CPRSET Pin Resistor
Min Typ Max
Unit Test Conditions/Comments
3.135 3.3 3.465 V
2.375
VS
V
VS
5.25
V
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
4.12
kΩ
Sets internal biasing currents; connect to ground
5.1
kΩ
Sets internal CP current range, nominally 4.8 mA
(CP_lsb = 600 µA); actual current can be calculated
by CP_lsb = 3.06/CPRSET; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled with
DC Offset Off)
Input Frequency (AC-Coupled with
DC Offset On)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled
with DC Offset Off)
Input Sensitivity (AC-Coupled with
DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
Pulse Width High/Low
Crystal Oscillator
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
Min Typ Max Unit Test Conditions/Comments
0
250
280
1.35 1.60 1.75
1.30 1.50 1.60
4.0
4.8 5.9
4.4
5.3 6.4
10
250
250
0
0.55
1.5
2.0
−100
2
1.8
250
3.28
2.78
0.8
+100
MHz
mV p-
p
V
V
kΩ
kΩ
MHz
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-
coupled; be careful to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing
slew rate (see Figure 11); the input sensitivity is
sufficient for ac-coupled LVDS and LVPECL signals
Self-bias voltage of REFIN1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate must be >50 V/µs
MHz
MHz
V p-p
Slew rate must be >50 V/µs, and input amplitude
sensitivity specification must be met; see the input
sensitivity parameter
Slew rate > 50 V/µs; CMOS levels
VIH should not exceed VS
V p-p VIH should not exceed VS
V
V
µA
pF
Each pin, REFIN (REF1)/REFIN (REF2)
ns
The amount of time that a square wave is high/low;
determines the allowable input duty cycle
16.62
33.33 MHz
30
Ω
Rev. B | Page 4 of 74
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