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AD9520-5

12 LVPECL/24 CMOS Output Clock Generator

Analog Devices 

Data Sheet

REVISION HISTORY

10/2016—Rev. A to Rev. B

Changed AD9520 to AD9520-5 .................................. Throughout

Change to PD Power-Down, Maximum Sleep Parameter,

Table 15.............................................................................................15

Updated Outline Dimensions........................................................74

8/2013—Rev. 0 to Rev. A

Changes to Features Section, Applications Section, and

General Description Section............................................................1

Changes to Table 2 ............................................................................4

Changes to Input Frequency Parameter; Change to Input

Sensitivity, Differential Parameter Test Conditions/Comments,

Table 3 .................................................................................................7

Change to Output Differential Voltage, VOD Parameter Test

Conditions/Comments; Added Source Current and Sink

Current Parameters, Table 4 ............................................................7

Reordered Figure 2 to Figure 4........................................................9

Change to Reset Timing, Pulse Width Low Parameter, Table 12...14

Change to Junction Temperature, Table 16; Reformatted

Table 16 ........................................................................................................ 16

Added NC Note to Figure 5; Change to Pin 4 and Pin 22

Description, Table 18 ......................................................................17

Reordered Figure 21 and Figure 22 ..............................................22

Added Figure 25, Renumbered Sequentially ...............................23

Change to Configuration of the PLL Section and Changes

to Charge Pump (CP) Section .......................................................30

Change to PLL Reference Inputs Section; Changes to

Reference Switchover Section........................................................31

Change to Prescaler Section and A and B Counters Section ....32

Changes to Table 25 ........................................................................33

Change to Clock Frequency Division Section; Changes to

VCO Divider Section; Added Channel Divider Maximum

Frequency Section ...........................................................................39

Reformatted Table 30 to Table 33..................................................40

Change to Phase Offset or Coarse Time Delay Section .............41

AD9520-5

Change to LVPECL Output Drivers Section; Changes to CMOS

Output Drivers Section and Power-On Reset Section ...............43

Changes to Soft Reset via the Serial Port Section and Soft

Reset to Settings in EEPROM when EEPROM Pin = 0b

via the Serial Port Section ..............................................................44

Change to Pin Descriptions Section and SPI Mode Operation

Section ..............................................................................................48

Changes to SPI Instruction Word (16 Bits) Section ...................49

Changes to EEPROM Operations Section, Writing to the

EEPROM Section, and Reading from the EEPROM Section ...52

Changes to Register Section Definition Group Section;

Added Operational Codes Section Heading ...............................53

Changes to Table 44 ........................................................................55

Added Unused Bits to Register Map Descriptions Section;

Changes to Address 0x000, Bit 5, and Added Address 0x003,

Table 45; Changes to Address 0x000, Bit 5, and Added

Address 0x003, Table 46 .................................................................58

Changes to Address 0x017, Bits[7:2], Table 48............................60

Changes to Address 0x018, Bit 4, Table 48 ..................................61

Changes to Address 0x01A, Bits[5:0], Setting 101010,

Table 48.............................................................................................62

Changes to Address 0x01B, Bits[4:0], Table 48 ...........................63

Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,

Table 50.............................................................................................66

Changes to Address 0x197, Bit 5, Table 50 ..................................67

Changes to Address 0x19A, Bit 5, Table 50 .................................68

Changes to Table 54 ........................................................................69

Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,

Table 55.............................................................................................70

Change to Frequency Planning Using the AD9520 Section .....71

Added LVPECL Y-Termination and Far-End Thevenin

Termination Headings; Changes to CMOS Clock Distribution

Section ..............................................................................................72

10/2008—Revision 0: Initial Version

Rev. B | Page 3 of 74

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