AD9520-1 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9520-1

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO

Analog Devices 

Timing Diagrams

tCLK

CLK

tPECL

tCMOS

Figure 2. CLK/CLK to Clock Output Timing, Div = 1

DIFFERENTIAL

80%

20%

LVPECL

tRP

tFP

Figure 3. LVPECL Timing, Differential

AD9520-1

SINGLE-ENDED

80%

20%

CMOS

10pF LOAD

tRC

tFC

Figure 4. CMOS Timing, Single-Ended, 10 pF Load

Rev. 0 | Page 9 of 84

Share Link: