AD9634 Ver la hoja de datos (PDF) - Analog Devices
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AD9634 Datasheet PDF : 31 Pages
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AD9634
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
LVDS Data and OR Outputs (OR+, OR−)
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ Max
CMOS/LVDS/LVPECL
0.9
0.3
3.6
AGND
AVDD
0.9
1.4
10
22
−22
−10
4
12
15
18
1.22
2.1
0
0.6
50
71
−5
+5
26
2
1.22
2.1
0
0.6
45
70
−5
+5
26
2
1.22
2.1
0
0.6
45
70
−5
+5
26
5
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
Full
250
350 450
mV
Full
1.15
1.25 1.35
V
Full
150
200 280
mV
Full
1.15
1.25 1.35
V
1 Pull-up.
2 Pull-down.
Rev. B | Page 6 of 30
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