AD9627(RevPrA) Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9627
(Rev.:RevPrA)

12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices 

AD9627

Preliminary Technical Data

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS

enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.

Table 1.

Parameter

RESOLUTION

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential

Nonlinearity (DNL)1

Integral Nonlinearity

(INL)1

TEMPERATURE DRIFT

Offset Error

Gain Error

INTERNAL VOLTAGE

REFERENCE

Output Voltage Error

(1 V Mode)

Load Regulation @ 1.0

mA

INPUT REFERRED NOISE

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 1.0

V

Input Capacitance2

VREF INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD, DVDD

DRVDD (CMOS

Mode)

Supply Current

IAVDD1

IDVDD1

IDRVDD1 (3.3V)

Temp

Full

Full

Full

Full

Full

25°C

Full

25°C

Full

Full

Full

Full

25°C

Full

Full

Full

Full

Full

Full

Full

Full

AD9627BCPZ-80

Min

Typ

Max

12

AD9627BCPZ-105

Min

Typ

Max

12

AD9627BCPZ-125

Min

Typ

Max

12

AD9627BCPZ-150

Min

Typ

Max

12

Unit

Bits

Guaranteed

±0.3

±2.0

±TBD

±TBD

±0.4

±TBD

±2

Guaranteed

±0.3 ±TBD

±2.0

±TBD

±0.4

±TBD

±1.8

Guaranteed

±0.3

±1.7

±TBD

±TBD

±0.4

±TBD

±2

Guaranteed

±0.3

±1.7

±TBD

±TBD

±0.4

±TBD

±2

% FSR

% FSR

LSB

LSB

LSB

LSB

±15

±15

±15

±95

±95

±95

±15

ppm/°C

±95

ppm/°C

TBD

TBD

TBD

TBD

TBD

TBD

TBD

mV

TBD

mV

TBD

TBD

TBD

2

2

2

8

8

8

6

6

6

TBD

LSB rms

2

V p-p

8

pF

6

kΩ

1.7

1.8

1.9 1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9 V

1.7

3.3

3.6 1.7

3.3

3.6

1.7

3.3

3.6

1.7

3.3

3.6 V

219

292

363

29

37

45

27

34

42

384

mA

47.5

mA

47.6

mA

IDRVDD1 (1.8V)

Full

PSRR

Full

POWER CONSUMPTION

DC Input

Full

Sine Wave Input1

Full

(DRVDD=1.8V)

Sine Wave Input1

Full

(DRVDD=3.3V)

Standby Power3

Full

Powerdown Power

Full

TBD

±0.01

TBD

TBD

536

TBD

TBD

TBD

±0.01

TBD

TBD

705

TBD

TBD

TBD

±0.01

TBD

TBD

873

TBD

TBD

TBD

±0.01

TBD

TBD

934

TBD

TBD

mA

% FSR

mW

mW

mW

mW

mW

1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.

3 Standby power is measured with a dc input, the CLK pins inactive (set to AVDD or AGND).

Rev. PrA | Page 4 of 40

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