AD9575 Ver la hoja de datos (PDF) - Analog Devices

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AD9575

Network Clock Generator, Two Outputs

Analog Devices 

AD9575

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter (Typ/Max)........................................ 4

LVPECL Clock Output Jitter (Typ/Max)................................... 4

Output Frequency Select ............................................................. 5

Clock Outputs ............................................................................... 5

Timing Characteristics ................................................................ 5

Power.............................................................................................. 6

Crystal Oscillator.......................................................................... 6

Timing Diagrams.......................................................................... 6

REVISION HISTORY

3/10—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Table 1, Table 2, and Table 3 ....................................... 4

Changes to Table 4 and Table 6....................................................... 5

Changes to Table 7 and Table 8....................................................... 6

Changes to Table 12.......................................................................... 8

Added Figure 11; Renumbered Figures Sequentially ................ 10

Changes to Figure 13...................................................................... 10

Changes to Theory of Operation Section and Figure 19........... 12

Changes to Figure 24...................................................................... 13

1/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................7

Thermal Resistance .......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics ..............................................9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump............ 12

Power Supply............................................................................... 12

LVPECL Clock Distribution ..................................................... 12

LVDS Clock Distribution .......................................................... 13

LVCMOS Clock Distribution ................................................... 13

Typical Application Circuit ....................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

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