AD9548(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD9548 Datasheet PDF : 112 Pages
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AD9548
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25°C; IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min
Typ Max Unit Test Conditions/Comments
3.135 3.30 3.465 V
1.71
1.80 1.89 V
3.135 3.30 3.465 V
3.135 3.30 3.465 V
1.71
1.80 1.89 V
1.71
1.80 1.89 V
Pin 7, Pin 82
Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
Pin 31, Pin 37, Pin 38, Pin 44
Pin 31, Pin 37, Pin 38, Pin 44
Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3.
The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3.
Table 2.
Parameter
SUPPLY CURRENT
IDVDD3
IDVDD
IAVDD3
IAVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
IAVDD
Min
Typ Max Unit Test Conditions/Comments
1.5
3
mA Pin 7, Pin 82
190 215 mA Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
52
75
mA Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
24
110 mA Pin 31, Pin 37, Pin 38, Pin 44
24
110 mA Pin 31, Pin 37, Pin 38, Pin 44
135 163 mA Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
All Blocks Running
Full Power-Down
Min Typ Max Unit Test Conditions/Comments
800
1100 mW
fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 122.88 MHz3; one
LVPECL clock distribution output running at 122.88 MHz
(all others powered down); one input reference running
at 100 MHz (all others powered down)
900
1400 mW
fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock
distribution outputs configured as LVPECL at 399 MHz; all
input references configured as differential at 100 MHz;
fractional-N active (R = 10, S = 39, U = 9, V = 10)
13
mW Conditions = typical configuration; no external pull-up or
pull-down resistors
Rev. 0 | Page 4 of 112
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