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componentes Descripción

Fabricante

AD9540BCPZ

655 MHz Low Jitter Clock Generator

Analog Devices 

AD9540

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND 1

AVDD 2

AGND 3

AVDD 4

IOUT 5

IOUT 6

AVDD 7

AGND 8

I/O_RESET 9

RESET 10

DVDD 11

DGND 12

PIN 1

INDICATOR

AD9540

TOP VIEW

(Not to Scale)

36 CP_OUT

35 CP_VDD

34 AGND

33 OUT0

32 OUT0

31 CP_VDD

30 AGND

29 CLK1

28 CLK1

27 AVDD

26 AGND

25 DVDD

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

1, 3, 8, 26, 30, AGND

34, 37, 43,

2, 4, 7, 27, 38, AVDD

44, 48

5

IOUT

6

IOUT

9

I/O_RESET

10

11, 25

12, 24

13

14

15

16

17

18

19

RESET

DVDD

DGND

SDO

SDI/O

SCLK

CS

DVDD_I/O

SYNC_OUT

SYNC_IN/STATUS

20

I/O_UPDATE

Figure 3. 48-Lead LFCSP Pin Configuration

Description

Analog Ground.

Analog Core Supply (1.8 V).

DAC Analog Output.

DAC Analog Complementary Output.

Resets the serial port when synchronization is lost in communications but does not reset the

device itself (active high). When not being used, this pin should be forced low, because it floats to

the threshold value.

Master Reset. Clears all accumulators and returns all registers to their default values (active high).

Digital Core Supply (1.8 V).

Digital Ground.

Serial Data Output. Used only when the device is programmed for 3-wire serial data mode.

Serial Data Input/Output. When the part is programmed for 3-wire serial data mode, this is input

only; in 2-wire mode, it serves as both the input and output.

Serial Data Clock. Provides the clock signal for the serial data port.

Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the

serial data clocks.

Digital Interface Supply (3.3 V).

Synchronization Clock Output.

Bidirectional Dual Function Pin. Depending on device programming, this pin is either the direct

digital synthesizer’s (DDS) synchronization input (allows alignment of multiple subclocks), or the PLL

lock detect output signal.

This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the

rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.

Rev. A | Page 10 of 32

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