AD9525 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9525

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

Data Sheet

AD9525

TIMING CHARACTERISTICS

Table 10.

Parameter

Min

PROPAGATION DELAY, tPECL, CLKIN TO LVPECL OUTPUT

For All M Divider Values

461

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS1

All LVPECL Outputs

Temperature Coefficient

All LVPECL Outputs Across Multiple Parts

OUTPUT SKEW, LVPECL-TO-SYNC_OUT1

SYNC_OUT LVPECL Mode

All LVPECL Outputs

Temperature Coefficient

All LVPECL Outputs Across Multiple Parts

SYNC_OUT CMOS Mode

All LVPECL Outputs

All LVPECL Outputs Across Multiple Parts

PROPAGATION DELAY, REF TO LVPECL OUTPUT

267

Typ Max

522 600

388

13.5 25.2

14

144

189 298

543

417

1.64 2.34

2.46

581 924

Unit Test Conditions/Comments

Termination as shown in Figure 35

ps High frequency clock distribution configuration

fs/°C

ps Across temperature and VDD per device

fs/°C

ps

ps Across temperature and VDD per device

fs/°C

ps

ns Across temperature and VDD per device

ns

ps REF refers to either REFA/REFA or REFB/REFB pairs

1 The output skew is the difference between any two paths while operating at the same voltage and temperature.

Timing Diagrams

tCLK

CLK

tPECL

tCMOS

Figure 2. CLK/CLK to Clock Output Timing, M Divider = 1

DIFFERENTIAL

80%

20%

LVPECL

tRP

tFP

Figure 3. LVPECL Timing, Differential

Rev. A | Page 7 of 48

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