AD9524 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9524

Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

Analog Devices 

Data Sheet

AD9524

TIMING ALIGNMENT CHARACTERISTICS

Table 10.

Parameter

OUTPUT TIMING SKEW

Between LVPECL, HSTL, and LVDS Outputs

Between CMOS Outputs

Adjustable Delay

Resolution Step

Zero Delay

Between Input Clock Edge on REFA or

REFB to ZD_IN Input Clock Edge,

External Zero Delay Mode

Min Typ Max Unit Test Conditions/Comments

Delay off on all outputs; maximum deviation

between rising edges of outputs; all outputs are on,

unless otherwise noted.

38 234 ps

100 300 ps Single-ended true phase high-Z mode

0

63 Steps Resolution step; for example, 8 × 0.5/1 GHz

500

ps ½ period of 1 GHz

150 500 ps

PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 μA, RZERO = 10 kΩ,

antibacklash pulse width is at maximum, BW = 40 Hz,

REFA and ZD_IN are set to differential mode

JITTER AND NOISE CHARACTERISTICS

Table 11.

Parameter

Min

OUTPUT ABSOLUTE RMS TIME JITTER

LVPECL Mode, HSTL Mode, LVDS Mode

Typ Max Unit

125

fs

136

fs

169

fs

212

fs

223

fs

Test Conditions/Comments

Application example based on a typical setup

(see Table 3); f = 122.88 MHz

Integrated BW = 200 kHz to 5 MHz

Integrated BW = 200 kHz to 10 MHz

Integrated BW = 12 kHz to 20 MHz

Integrated BW = 10 kHz to 61 MHz

Integrated BW = 1 kHz to 61 MHz

PLL2 CHARACTERISTICS

Table 12.

Parameter

VCO (ON CHIP)

Frequency Range

Gain

PLL2 FIGURE OF MERIT (FOM)

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Minimum and Low

Maximum and High

Min Typ Max Unit

Test Conditions/Comments

3600

45

−226

4000

MHz

MHz/V

dBc/Hz

250 MHz

125 MHz

Rev. D | Page 9 of 56

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