AD9524 Ver la hoja de datos (PDF) - Analog Devices
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AD9524 Datasheet PDF : 56 Pages
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AD9524
Data Sheet
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
Min Typ
559
Max Unit
593 mW
PD, Power-Down
INCREMENTAL POWER DISSIPATION
Low Power Typical Configuration
Switched to One Input,
Reference Single-Ended Mode
Switched to Two Inputs,
Reference Differential Mode
Switched to Two Inputs,
Reference Single-Ended Mode
Output Distribution, Driver On
LVDS
LVPECL Compatible
HSTL
CMOS
101 132.2 mW
389 450.4 mW
−28.5 −8
mW
26
44.6 mW
−27.5 −5.1 mW
15.3 18.4 mW
47.8 55.4 mW
50.1 54.9 mW
40.2 46.3 mW
43.7 50.3 mW
6.6
7.9
mW
9.9
11.9 mW
9.9
11.9 mW
Test Conditions/Comments
Clock distribution outputs running as follows: four LVPECL outputs
at 122.88 MHz, two LVDS outputs (3.5 mA) at 122.88 MHz,
one differential input reference at 30.72 MHz; fVCXO = 122.88 MHz,
fVCO = 3932.16 MHz; PLL2 BW = 530 kHz; doubler is off
PD pin pulled low, with typical configuration conditions
Absolute total power with clock distribution; one LVPECL output
running at 122.88 MHz; one differential input reference at
30.72 MHz; fVCXO = 122.88 MHz, fVCO = 3932.16 MHz; doubler is off
Running at 30.72 MHz
Running at 30.72 MHz
Running at 30.72 MHz
Incremental power increase (OUT1) from low power typical (3.3 V)
Single 3.5 mA LVDS output at 245.76 MHz
Single 7 mA LVDS output at 61.44 MHz
Single LVPECL output at 122.88 MHz
Single 8 mA HSTL output at 122.88 MHz
Single 16 mA HSTL output at 122.88 MHz
Single 3.3 V CMOS output at 15.36 MHz
Dual complementary 3.3 V CMOS output at 15.36 MHz
Dual in-phase 3.3 V CMOS output at 15.36 MHz
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS
Table 4.
Parameter
Min Typ
DIFFERENTIAL MODE
Input Frequency Range
Input Slew Rate (OSC_IN)
400
Common-Mode Internally
Generated Input Voltage
0.6 0.7
Input Common-Mode Range
1.025
Differential Input Voltage,
100
Sensitivity Frequency < 250 MHz
Differential Input Voltage,
200
Sensitivity Frequency > 250 MHz
Differential Input Resistance
4.8
Differential Input Capacitance
1
Duty Cycle
Pulse Width Low
1
Pulse Width High
1
CMOS MODE SINGLE-ENDED INPUT
Input Frequency Range
Input High Voltage
1.6
Input Low Voltage
Input Threshold Voltage
1.0
Max Unit Test Conditions/Comments
400 MHz
V/µs Minimum limit imposed for jitter performance
0.8
V
1.475
V
mV p-p
mV p-p
kΩ
pF
ns
ns
For dc-coupled LVDS (maximum swing)
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Duty cycle bounds are set by pulse width high and pulse width low
250 MHz
V
0.52 V
V
When ac coupling to the input receiver, the user must dc bias the
input to 1 V; the single-ended CMOS input is 3.3 V compatible
Rev. D | Page 6 of 56
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