AD9524 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9524

Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

Analog Devices 

Data Sheet

AD9524

Parameter

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

Clock Rate (SCLK, 1/tSCLK)

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup, tS

CS to SCLK Setup and Hold, tS, tC

CS Minimum Pulse Width High, tPWH

Min

Typ Max

Unit Test Conditions/Comments

2.7

V

0.4

V

25

MHz

8

ns

12

ns

3.3

ns

0

ns

14

ns

10

ns

0

ns

6

ns

SERIAL CONTROL PORT—I²C MODE

VDD = VDD3_REF, unless otherwise noted.

Table 16.

Parameter

SDA, SCL (WHEN INPUTTING DATA)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Current with an Input Voltage Between

0.1 × VDD and 0.9 × VDD

Hysteresis of Schmitt Trigger Inputs

Pulse Width of Spikes That Must Be

Suppressed by the Input Filter, tSPIKE

SDA (WHEN OUTPUTTING DATA)

Output Logic 0 Voltage at 3 mA Sink Current

Output Fall Time from VIHMIN to VILMAX with

a Bus Capacitance from 10 pF to 400 pF

TIMING

Min

Typ

0.7 × VDD

−10

0.015 × VDD

20 + 0.1 CB1

Max

Unit

V

0.3 × VDD V

+10

µA

V

50

ns

0.4

V

250

ns

Clock Rate (SCL, fI2C)

Bus Free Time Between a Stop and Start

1.3

Condition, tIDLE

Setup Time for a Repeated Start Condition, 0.6

tSET; STR

Hold Time (Repeated) Start Condition, tHLD; STR 0.6

400

kHz

µs

µs

µs

Setup Time for Stop Condition, tSET; STP

Low Period of the SCL Clock, tLOW

High Period of the SCL Clock, tHIGH

SCL, SDA Rise Time, tRISE

SCL, SDA Fall Time, tFALL

Data Setup Time, tSET; DAT

Data Hold Time, tHLD; DAT

0.6

1.3

0.6

20 + 0.1 CB1

20 + 0.1 CB1

100

100

µs

µs

µs

300

ns

300

ns

ns

880

ns

Capacitive Load for Each Bus Line, CB1

400

pF

Test Conditions/Comments

Note that all I2C timing values are referred to

VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)

After this period, the first clock pulse is

generated

This is a minor deviation from the original I²C

specification of 0 ns minimum2

1 CB is the capacitance of one bus line in picofarads (pF).

2 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL

falling edge.

Rev. D | Page 11 of 56

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