AD9523BCPZ Ver la hoja de datos (PDF) - Analog Devices
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Fabricante
AD9523BCPZ
Analog Devices
AD9523BCPZ Datasheet PDF : 60 Pages
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Data Sheet
AD9523
LOGIC INPUT PINS—PD, EEPROM_SEL, REF_SEL, RESET, SYNC
Table 13.
Parameter
VOLTAGE
Input High
Input Low
INPUT LOW CURRENT
Min
Typ
Max
2.0
0.8
±80
±250
CAPACITANCE
3
RESET TIMING
Pulse Width Low
50
Inactive to Start of Register Programming 100
SYNC TIMING
Pulse Width Low
1.5
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 14.
Parameter
VOLTAGE
Output High
Output Low
Min
Typ
Max
2.94
0.4
SERIAL CONTROL PORT—SPI MODE
Table 15.
Parameter
Min
CS (INPUT)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Typ Max
2.0
0.8
30
−110
Input Capacitance
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
2
2.0
0.8
240
1
2
2.0
0.8
1
1
2
Rev. D | Page 9 of 60
Unit Test Conditions/Comments
V
V
µA
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing
out of the AD9523
pF
ns
ns
ns
High speed clock is CLK input signal
Unit Test Conditions/Comments
V
V
Unit Test Conditions/Comments
CS has an internal 40 kΩ pull-up resistor
V
V
µA
µA
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9523
pF
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
V
V
µA
µA
pF
V
V
µA
µA
pF
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