AD9523BCPZ Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9523BCPZ

Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

Analog Devices 

AD9523

OSC_CTRL OUTPUT CHARACTERISTICS

Table 5.

Parameter

OUTPUT VOLTAGE

High

Low

Min

Typ

Max

VDD3_PLL1 − 0.15

150

REF_TEST INPUT CHARACTERISTICS

Table 6.

Parameter

Min

REF_TEST INPUT

Input Frequency Range

Input High Voltage

2.0

Typ

Max

250

Input Low Voltage

0.8

PLL1 CHARACTERISTICS

Table 7.

Parameter

Min

PLL1 FIGURE OF MERIT (FOM)

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Typ

Max

−226

Minimum

130

Low

90

High

65

Maximum

45

PLL1 OUTPUT CHARACTERISTICS

Table 8.

Parameter1

Min

Typ

Max

MAXIMUM OUTPUT FREQUENCY

250

Rise/Fall Time (20% to 80%)

387

665

Duty Cycle

45

50

55

OUTPUT VOLTAGE HIGH

VDD3_PLL1 − 0.25

VDD3_PLL1 − 0.1

OUTPUT VOLTAGE LOW

0.2

0.1

1 CMOS driver strength = strong (see Table 52).

Data Sheet

Unit Test Conditions/Comments

V

RLOAD > 20 kΩ

mV

Unit Test Conditions/Comments

MHz

V

V

Unit Test Conditions/Comments

dBc/Hz

High is the initial PLL1 antibacklash pulse

width setting. The user must program

Register 0x019[4] = 1b to enable SPI

control of the antibacklash pulse width to

the setting defined in Register 0x019[3:2]

and Table 40.

MHz

MHz

MHz

MHz

Unit Test Conditions/Comments

MHz

ps

15 pF load

%

f = 250 MHz

Output driver static

V

Load current = 10 mA

V

Load current = 1 mA

Output driver static

V

Load current = 10 mA

V

Load current = 1 mA

Rev. D | Page 6 of 60

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