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AD9445

14-Bit, 105/125 MSPS, IF Sampling ADC

Analog Devices 

AD9445

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal

trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.

Table 1.

Parameter

RESOLUTION

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)1

Integral Nonlinearity (INL)1

VOLTAGE REFERENCE

Output Voltage VREF = 1.0 V

Load Regulation @ 1.0 mA

Reference Input Current (External VREF = 1.6 V)

INPUT REFERRED NOISE

ANALOG INPUT

Input Span

VREF = 1.6 V

VREF = 1.0 V

Internal Input Common-Mode Voltage

External Input Common-Mode Voltage

Input Resistance2

Input Capacitance2

POWER SUPPLIES

Supply Voltage

AVDD1

AVDD2

DRVDD—LVDS Outputs

DRVDD—CMOS Outputs

Supply Current1

AVDD1

AVDD21, 3

IDRVDD1—LVDS Outputs

IDRVDD1—CMOS Outputs

PSRR

Offset

Gain

POWER CONSUMPTION

LVDS Outputs

CMOS Outputs (DC Input)

AD9445BSVZ-105

AD9445BSVZ-125

Temp Min Typ

Max Min Typ

Max Unit

Full

14

14

Bits

Full

Guaranteed

Guaranteed

Full

−7

+7

−7

+7

mV

25°C

±3

±3

mV

Full

−3

+3

−3

+3

% FSR

25°C

−2

+2

−2

+2

% FSR

Full

−0.6 ±0.25 +0.65 −0.6 ±0.25 +0.65 LSB

5

5

25°C

±0.65

±0.8

LSB

Full

−1.6

+1.6 −2

+2

LSB

Full

0.9 1.0

Full

±2

Full

25°C

1.0

1.1

0.9

1.0

±2

1.0

1.1

V

mV

μA

LSB rms

Full

3.2

3.2

V p-p

Full

2.0

2.0

V p-p

Full

3.5

3.5

V

Full

3.1

3.9

3.1

3.9

V

Full

1

1

kΩ

Full

6

6

pF

Full

3.14 3.3

3.46 3.14 3.3

3.46 V

Full

4.75 5.0

5.25 4.75 5.0

5.25 V

Full

3.0

3.6

3.0

3.6

V

Full

3.0 3.3

3.6

3.0

3.3

3.6

V

Full

335

364

384

424 mA

Full

169

196

172

199 mA

Full

63

78

63

78

mA

Full

14

14

mA

Full

1

Full

0.2

1

mV/V

0.2

%/V

Full

2.2

2.4

2.3

2.6

W

Full

2.0

2.1

W

1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.

Rev. 0 | Page 3 of 40

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