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AD9444

14-Bit, 80 MSPS, A/D Converter

Analog Devices 

AD9444

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No.

Mnemonic Description

Pin No.

1, 8 to 9,

16 to 18,

24 to 27,

34 to 35, 38,

41 to 42, 87,

89 to 95, 98

2 to 4

AVDD1

DNC

5

OUTPUT

MODE

6

DFS

7

LVDSBIAS

10

SENSE

3.3 V (±5%) Analog Supply.

Do Not Connect. These pins

should float.

CMOS Compatible Output Logic

Mode Control Pin. OUTPUT MODE

= 0 for CMOS mode, and OUTPUT

MODE = 1 (AVDD1) for LVDS

outputs.

Data Format Select Pin. CMOS

control pin that determines the

format of the output data. DFS =

high (AVDD1) for twos comple-

ment, DFS = low (ground) for

offset binary format.

Set Pin for LVDS Output Current.

Place 3.7 kΩ resistor terminated to

DRGND.

Reference Mode Selection.

Connect to AGND for internal 1 V

reference, and connect to AVDD2

for external reference.

44

45

46

47, 54, 62,

75, 83

48, 53, 61,

67, 74, 82

49

50

51

52

55

56

57

58

59

60

63

64

65

66

68

69

11

VREF

1.0 V Reference I/O—Function

70

Dependent on SENSE. Decouple

71

to ground with 0.1 µF and 10 µF

72

capacitors.

73

12, 15, 20,

23, 32, 86,

AGND

Analog Ground. The exposed

heat sink on the bottom of the

76

88, 96 to 97,

package must be connected to

77

99, Exposed

AGND.

78

Heat Sink

79

13

REFT

Differential Reference Output.

80

Decoupled to ground with 0.1 µF

81

capacitor and to REFB (Pin 14) with

0.1 µF and 10 µF capacitors.

84

14

REFB

Differential Reference Output.

Decoupled to ground with a 0.1 µF

85

capacitor and to REFT (Pin 13) with

100

0.1 µF and 10 µF capacitors.

19, 28 to 31, AVDD2

39 to 40

5.0 V Analog Supply (±5%).

21

VIN+

Analog Input—True.

22

VIN−

Analog Input—Complement.

33

C1

Internal Bypass Node. Connect a

0.1 µF capacitor from this pin

to AGND.

36

CLK+

Clock Input—True.

37

CLK−

Clock Input—Complement.

43

D0− (LSB) D0 Complement Output Bit

(LVDS Levels).

Mnemonic

D0+

D1−

D1+

DRVDD

DRGND

Description

D0 True Output Bit.

D1 Complement Output Bit.

D1 True Output Bit.

3.3 V Digital Output Supply

(3.0 V to 3.6 V).

Digital Ground.

D2−

D2+

D3−

D3+

D4−

D4+

D5−

D5+

D6−

D6+

DCO−

DCO+

D7−

D7+

D8−

D8+

D9−

D9+

D10−

D10+

D11−

D11+

D12−

D12+

D13−

D13+ (MSB)

OR−

OR+

DCS MODE

D2 Complement Output Bit.

D2 True Output Bit.

D3 Complement Output Bit.

D3 True Output Bit.

D4 Complement Output Bit.

D4 True Output Bit.

D5 Complement Output Bit.

D5 True Output Bit.

D6 Complement Output Bit.

D6 True Output Bit.

Data Clock Output—Complement.

Data Clock Output—True.

D7 Complement Output Bit.

D7 True Output Bit.

D8 Complement Output Bit.

D8 True Output Bit.

D9 Complement Output Bit.

D9 True Output Bit.

D10 Complement Output Bit.

D10 True Output Bit.

D11 Complement Output Bit.

D11 True Output Bit.

D12 Complement Output Bit.

D12 True Output Bit.

D13 Complement Output.

D13 True Output Bit.

Out-of-Range Complement

Output Bit.

Out-of-Range True Output Bit.

Clock Duty Cycle Stabilizer (DCS)

Control Pin, CMOS-Compatible.

DCS = low (AGND) to enable DCS

(recommended). DCS = high

(AVDD1) to disable DCS.

Rev. 0 | Page 11 of 40

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