AD9433(RevA) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9433
(Rev.:RevA)

12-Bit, 105 MSPS/125 MSPS, IF Sampling ADC

Analog Devices 

AD9433

–95

WORST OTHER (dBc)

–90

THIRD HARMONIC (dBc)

–85

–80

SECOND HARMONIC (dBc)

–75

–70

SNR (dB)

–65

0

10 20 30 40 50 60 70 80 90

DUTY CYCLE HIGH (%)

Figure 16. Dynamic Performance vs. Encode Duty Cycle, fS = 105 MSPS,

fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

0

512 1024 1536 2048 2560 3072 3584 4096

OUTPUT CODE

Figure 17. Integral Nonlinearity vs. Output Code with SFDR Mode Disabled

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

512 1024 1536 2048 2560 3072 3584 4096

OUTPUT CODE

Figure 18. Differential Nonlinearity vs. Output Code

300

18

280

15

260

12

ICC (mA)

240

9

220

6

IDD (mA)

200

3

180

0

0

25

50

75

100

125

ENCODE FREQUENCY (MHz)

Figure 19. IDD and ICC vs. Encode Rate, fIN = 10.3 MHz,

Differential AIN @ −0.5 dBFS

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

0

512 1024 1536 2048 2560 3072 3584 4096

OUTPUT CODE

Figure 20. Integral Nonlinearity vs. Output Code with SFDR Mode Enabled

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

7.68

15.36

23.04

FREQUENCY (MHz)

30.72

Figure 21. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, Four WCDMA Carriers,

Differential AIN, SFDR Mode Enabled

Rev. A | Page 10 of 20

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