AD9398 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD9398 Datasheet PDF : 44 Pages
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Pin Type
POWER SUPPLY
CONTROL
HDCP
AUDIO DATA OUTPUTS
DATA ENABLE
RTERM
AD9398
Pin No.
80, 76, 72, 67, 45, 33
100, 90, 10
59, 56, 54
48, 32, 30
83
82
49
50
51
52
28
27
26
25
24
20
21
22
23
88
46
Mnemonic
VD
VDD
PVDD
DVDD
GND
SDA
SCL
DDCSCL
DDCSDA
MCL
MDA
S/PDIF
I2S0
I2S1
I2S2
I2S3
MCLKIN
MCLKOUT
SCLK
LRCLK
DE
RTERM
Function
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
S/PDIF Digital Audio Output
I2S Audio (Channel 1, Channel 2)
I2S Audio (Channel 3, Channel 4)
I2S Audio (Channel 5, Channel 6)
I2S Audio (Channel 7, Channel 8)
External Reference Audio Clock In
Audio Master Clock Output
Audio Serial Clock Output
Data Output Clock for Left and Right Audio Channels
Data Enable
Sets Internal Termination Resistance
Value
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
3.3 V CMOS
500 Ω
Table 6. Pin Function Descriptions
Mnemonic
Description
INPUTS
Rx0+
Digital Input Channel 0 True.
Rx0−
Digital Input Channel 0 Complement.
Rx1+
Digital Input Channel 1 True.
Rx1−
Digital Input Channel 1 Complement.
Rx2+
Digital Input Channel 2 True.
Rx2−
Digital input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel
rate) from a digital graphics transmitter.
RxC+
Digital Data Clock True.
RxC−
Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
FILT
External Filter Connection.
For proper operation, the audio-clock generator PLL requires an external filter. Connect the filter shown in Figure 8
to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the
PCB Layout Recommendations section .
PWRDN
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
OUTPUTS
HSOUT
Horizontal Sync Output.
A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can
be programmed via serial bus registers. By maintaining alignment with DATACK and DATA, data timing with
respect to horizontal sync can always be determined.
VSOUT
Vertical Sync Output.
The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this
output can be controlled via the serial bus bit (Register 0x24 [6]).
O/E FIELD
Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is
odd or even. The polarity of this signal is programmable via Register 0x24[4].
DE
Data Enable that defines valid video. Can be received in the signal or generated by the AD9398.
Rev. 0 | Page 7 of 44
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