AD9389B Ver la hoja de datos (PDF) - Analog Devices
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AD9389B Datasheet PDF : 12 Pages
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Preliminary Technical Data
Table 3. Pin Function Descriptions
Pin No.
LFCSP
LQFP
Mnemonic
2, 39 to 47,
50 to 63
2, 50 to 58,
65 to 78
D[23:0]
6
6
CLK
3
3
DE
4
4
5
5
18
23
HSYNC
VSYNC
EXT_SWG
20
25
HPD
7
7
S/PDIF
8
8
MCLK
9 to 12
13
14
262
9 to 12
13
14
332
I2S[3:0]
SCLK
LRCLK
PD/A0
21, 22
30, 31
27, 28
24, 25
32
19, 23, 29
1, 48, 49
15 to 17
27, 28
37, 38
34, 35
30, 31
40
24, 29, 36, 41
1, 61 to 64
16, 19 to 21
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
DVDD
PVDD
64, paddle
on bottom
side
36
35
37
38
15, 17, 18, 22, GND
26, 32, 39, 42,
43, 59, 60, 79, 80
47
SDA
46
SCL
48
MDA
49
MCL
AD9389B
Type 1
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
P
P
P
C2
C2
C2
C2
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic
levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to
3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place an 887 Ω resistor (1% tolerance)
between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is
connected. 1.8 V to 5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input
from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 ×
sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. Supports 1.8 V to 3.3 V
CMOS logic level.
I2S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD
polarity are set by the PD/A0 pin state when the supplies are applied to the
AD9389B. Supports 1.8 V to 3.3 V CMOS logic level.
Differential Clock Output. Differential clock output at pixel clock rate; TMDS
logic level.
Differential Output Channel 2. Differential output of the red data at 10× the
pixel clock rate; TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10× the
pixel clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the
pixel clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply
is recommended.
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power
to the digital logic and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the
clock generation circuitry. These pins provide power to the clock PLL. The
designer should provide quiet, noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that
the AD9389B be assembled on a single, solid ground plane with careful
attention given to ground current paths.
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic
levels from 1.8 V to 3.3 V.
Rev. PrA | Page 7 of 12
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