AD9380 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9380

Analog/HDMI Dual-Display Interface

Analog Devices 

AD9380

Pin Type

OUTPUTS

REFERENCES

POWER SUPPLY

CONTROL

HDCP

AUDIO DATA OUTPUTS

DIGITAL VIDEO DATA

DIGITAL VIDEO CLOCK

INPUTS

DATA ENABLE

RTERM

Pin No.

92 to 99

2 to 9

12 to 19

89

87

85

86

84

57

80, 76, 72,

67, 45, 33

100, 90, 10

59, 56, 54

48, 32, 30

82

83

49

50

51

52

28

27

26

25

24

20

21

22

23

34

35

37

38

40

41

43

44

88

46

Mnemonic

RED [7:0]

GREEN [7:0]

BLUE [7:0]

DATACK

HSOUT

VSOUT

SOGOUT

O/E FIELD

FILT

VD

VDD

PVDD

DVDD

GND

SCL

SDA

DDCSCL

DDCSDA

PU2

PU1

S/PDIF

I2S0

I2S1

I2S2

I2S3

MCLKIN

MCLKOUT

SCLK

LRCLK

Function

Outputs of Red Converter, Bit 7 is MSB

Outputs of Green Converter, Bit 7 is MSB

Outputs of Blue Converter, Bit 7 is MSB

Data Output Clock

HSYNC Output Clock (Phase-Aligned with DATACK)

VSYNC Output Clock (Phase-Aligned with DATACK)

SOG Slicer Output

Odd/Even Field Output

Connection for External Filter Components For PLL

Analog Power Supply and DVI Terminators

Output Power Supply

PLL Power Supply

Digital Logic Power Supply

Ground

Serial Port Data Clock

Serial Port Data I/O

HDCP Slave Serial Port Data Clock

HDCP Slave Serial Port Data I/O

Should be tied to 3.3 V through a 10 kΩ resistor

Should be tied to 3.3 V through a 10 kΩ resistor

S/PDIF Digital Audio Output

I2S Audio (Channel 1, Channel 2)

I2S Audio (Channel 3, Channel 4)

I2S Audio (Channel 5, Channel 6)

I2S Audio (Channel 7, Channel 8)

External Reference Audio Clock In

Audio Master Clock Output

Audio Serial Clock Output

Data Output Clock for Left And Right Audio Channels

Rx0−

Rx0+

Rx1−

Rx1+

Rx2−

Rx2+

RxC+

RxC−

DE

RTERM

Digital Input Channel 0 Complement

Digital Input Channel 0 True

Digital Input Channel 1 Complement

Digital Input Channel 1 True

Digital Input Channel 2 Complement

Digital Input Channel 2 True

Digital Data Clock True

Digital Data Clock Complement

Data Enable

Sets Internal Termination Resistance

Value

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

3.3 V

1.8 V to 3.3 V

1.8 V

1.8 V

0V

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

TMDS

TMDS

TMDS

TMDS

TMDS

TMDS

3.3 V CMOS

500 Ω

Rev. 0 | Page 8 of 60

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