AD9250(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9250
(Rev.:Rev0)

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter

Analog Devices 

AD9250

Data Sheet

SWITCHING SPECIFICATIONS

Table 4.

Parameter

CLOCK INPUT PARAMETERS

Conversion Rate1

SYSREF± Setup Time to Rising Edge CLK±2

SYSREF± Hold Time from Rising Edge CLK±2

CLK± Pulse Width High

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-2 Mode Through Divide-by-8 Mode

Aperture Delay

Aperture Uncertainty (Jitter)

DATA OUTPUT PARAMETERS

Data Output Period or Unit Interval (UI)

Data Output Duty Cycle

Data Valid Time

PLL Lock Time (tLOCK)

Wake-Up Time

Standby

ADC (Power-Down)3

Output (Power-Down)4

SYNCINB± Falling Edge to First K.28 Characters

CGS Phase K.28 Characters Duration

Pipeline Delay

JESD204B M1, L1 Mode (Latency)

JESD204B M1, L2 Mode (Latency)

JESD204B M2, L1 Mode (Latency)

JESD204B M2, L2 Mode (Latency)

Fast Detect (Latency)

Data Rate per Lane

Uncorrelated Bounded High Probability (UBHP) Jitter

Random Jitter

At 3.4 Gbps

At 5.0 Gbps

Output Rise/Fall Time

Differential Termination Resistance

Out-of-Range Recovery Time

AD9250-170

AD9250-250

Symbol Temperature Min Typ Max Min Typ Max Unit

fS

tSYSR_S

tSYSR_H

tCH

tA

tJ

Full

Full

Full

Full

Full

Full

Full

Full

Full

25°C

25°C

25°C

40

170 40

250 MSPS

0.75

0.75

ns

0

0

ns

2.61 2.9 3.19 1.8

2.76 2.9 3.05 1.9

0.8

0.8

1.0

0.16

2.0 2.2

2.0 2.1

1.0

0.16

ns

ns

ns

ns

ps rms

L/(20 × M × fS)

50

0.84

25

L/(20 × M × fS)

50

0.78

25

Seconds

%

UI

µs

25°C

10

10

µs

25°C

250

250

µs

25°C

50

50

µs

Full

4

4

Multiframes

Full

1

1

Multiframe

Full

36

36

Cycles5

Full

59

59

Cycles

Full

25

25

Cycles

Full

36

36

Cycles

Full

7

7

Cycles

Full

3.4 5.0

5.0 Gbps

Full

6

8

ps

Full

2.3

ps rms

Full

1.7

ps rms

Full

60

60

ps

25°C

100

100

Ω

Full

3

3

Cycles

1 Conversion rate is the clock rate after the divider.

2 Refer to Figure 3 for timing diagram.

3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.

4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.

5 Cycles refers to ADC conversion rate cycles.

Rev. 0 | Page 8 of 44

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