AD9238BSTZRL-40(RevC) Ver la hoja de datos (PDF) - Analog Devices
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AD9238BSTZRL-40 Datasheet PDF : 48 Pages
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AD9238
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS1
High Level Output Voltage
Low Level Output Voltage
Test
AD9238BST/BCP-20
AD9238BST/BCP-40
AD9238BST/BCP-65
Temp Level Min
Typ Max Min
Typ Max Min
Typ Max Unit
Full IV
2.0
Full IV
Full IV
−10
Full IV
−10
Full IV
2.0
0.8
+10 −10
+10 −10
2
2.0
0.8
+10 −10
+10 −10
2
V
0.8 V
+10 μA
+10 μA
2
pF
Full IV
Full IV
DRVDD −
0.05
DRVDD −
0.05
0.05
DRVDD −
0.05
0.05
V
0.05 V
1 Output voltage levels measured with capacitive load only on each output.
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High1
CLK Pulse-Width Low1
DATA OUTPUT PARAMETER
Output Delay2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
Full VI
20
Full V
Full V
50.0
Full V
15.0
Full V
15.0
40
1
25.0
8.8
8.8
65
1
15.4
6.2
6.2
MSPS
1
MSPS
ns
ns
ns
Full VI
2
3.5 6
2
3.5 6
2
3.5 6
ns
Full V
7
7
7
Cycles
Full V
1.0
1.0
1.0
ns
Full V
0.5
0.5
0.5
ps rms
Full V
2.5
2.5
2.5
ms
Full V
2
2
2
Cycles
1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N
N+1
N+2
N+8
N–1
ANALOG
INPUT
N+3
N+4
N+7
N+5
N+6
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
Figure 2. Timing Diagram
N
tPD = MIN 2.0ns,
MAX 6.0ns
Rev. C | Page 6 of 48
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