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AD9238-65PCB(RevA) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza
componentes Descripción
Fabricante
AD9238-65PCB
(Rev.:RevA)
ADI
Analog Devices ADI
AD9238-65PCB Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9238
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AGND 1
VIN+_A 2
VIN–_A 3
AGND 4
AVDD 5
REFT_A 6
REFB_A 7
VREF 8
SENSE 9
REFB_B 10
REFT_B 11
AVDD 12
AGND 13
VIN–_B 14
VIN+_B 15
AGND 16
PIN 1
IDENTIFIER
AD9238
64-LEAD LQFP
TOP VIEW
(Not to Scale)
48 D4_A
47 D3_A
46 D2_A
45 D1_A
44 D0_A
43 DNC
42 DNC
41 DRVDD
40 DRGND
39 OTR_B
38 D11_B (MSB)
37 D10_B
36 D9_B
35 D8_B
34 D7_B
33 D6_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Number
2
3
15
14
6
7
11
10
8
9
18
63
19
20
21
60
22
59
44–51, 54–57
25–27, 30–38
39
58
62
61
5, 12, 17, 64
1, 4, 13, 16
28, 40, 53
29, 41, 52
23, 24, 42, 43
DNC = DO NOT CONNECT
Mnemonic
VIN+_A
VIN–_A
VIN+_B
VIN–_B
REFT_A
REFB_A
REFT_B
REFB_B
VREF
SENSE
CLK_B
CLK_A
DCS
DFS
PDWN_B
PDWN_A
OEB_B
OEB_A
D0_A (LSB)–D11_A (MSB)
D0_B (LSB)–D11_B (MSB)
OTR_B
OTR_A
SHARED_REF
MUX_SELECT
AVDD
AGND
DRGND
DRVDD
DNC
PIN FUNCTION DESCRIPTIONS
Description
Analog Input Pin (+) for Channel A
Analog Input Pin (–) for Channel A
Analog Input Pin (+) for Channel B
Analog Input Pin (–) for Channel B
Differential Reference (+) for Channel A
Differential Reference (–) for Channel A
Differential Reference (+) for Channel B
Differential Reference (–) for Channel B
Voltage Reference Input/Output
Reference Mode Selection
Clock Input Pin for Channel B
Clock Input Pin for Channel A
Enable Duty Cycle Stabilizer (DCS) Mode
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)
Power-Down Function Selection for Channel B (Active High)
Power-Down Function Selection for Channel A (Active High)
Output Enable Bit for Channel B
Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
Channel A Data Output Bits
Channel B Data Output Bits
Out-of-Range Indicator for Channel B
Out-of-Range Indicator for Channel A
Shared Reference Control Bit (Low for Independent Reference Mode,
High for Shared Reference Mode)
Data Multiplexed Mode. (See description for how to enable; high setting disables
output data Multiplexed mode).
Analog Power Supply
Analog Ground
Digital Output Ground
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum
0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.
Do Not Connect Pins. Should be left floating.
–6–
REV. A

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