AD9233BCPZRL7-105 Ver la hoja de datos (PDF) - Analog Devices
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AD9233BCPZRL7-105 Datasheet PDF : 44 Pages
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AD9233
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter1
CLOCK INPUT PARAMETERS
Conversion Rate, DCS Enabled
Conversion Rate, DCS Disabled
CLK Period
CLK Pulse Width High, DCS Enabled
CLK Pulse Width High, DCS Disabled
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE4
SCLK Period (tCLK)
SCLK Pulse Width High Time (tHI)
SCLK Pulse Width Low Time (tLO)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
AD9233BCPZ-80
Temp Min Typ Max
Full
20
80
Full
10
80
Full
12.5
Full
3.75 6.25 8.75
Full
5.63 6.25 6.88
Full
3.1 3.9 4.8
Full
4.4
Full
4.9 5.7
Full
5.9 6.8
Full
12
Full
0.8
Full
0.1
Full
350
Full
2
Full
40
Full
16
Full
16
Full
5
Full
2
Full
5
Full
2
AD9233BCPZ-105
Min Typ Max
20
105
10
105
9.5
2.85 4.75 6.65
4.28 4.75 5.23
3.1 3.9 4.8
4.4
3.4 4.3
4.4 5.3
12
0.8
0.1
350
2
40
16
16
5
2
5
2
AD9233BCPZ-125
Min Typ Max
20
125
10
125
8
2.4 4
5.6
3.6 4
4.4
3.1 3.9 4.8
4.4
2.6 3.5
3.7 4.5
12
0.8
0.1
350
3
40
16
16
5
2
5
2
1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependant on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
4 See Figure 57 and the Serial Port Interface (SPI) section.
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
cycles
ns
ps rms
ms
cycles
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM
CLK+
CLK–
DATA
DCO
N+1 N+2
N
tA
tCLK
N+ 3
N+4
N+ 5
N+ 6
N+ 7
N+ 8
tPD
N – 13 N – 12 N – 11
tS
tH
N – 10 N – 9
tDCO
N–8
N–7
tCLK
N–6
N–5 N–4
Figure 2. Timing Diagram
Rev. A | Page 7 of 44
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