AD9231-20EBZ(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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AD9231-20EBZ
(Rev.:Rev0)

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices 

AD9231

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 4.

Parameter

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate1

CLK Period—Divide-by-1 Mode (tCLK)

CLK Pulse Width High (tCH)

Aperture Delay (tA)

Aperture Uncertainty (Jitter, tJ)

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

DCO Propagation Delay (tDCO)

DCO to Data Skew (tSKEW)

Pipeline Delay (Latency)

Wake-Up Time2

Standby

OUT-OF-RANGE RECOVERY TIME

AD9231-20/AD9231-40

Temp Min Typ

Max

AD9231-65

AD9231-80

Min Typ Max Min Typ Max

Full

625

625

625

Full 3

20/40 3

65 3

80

Full 50/25

15.38

12.5

25.0/12.5

7.69

6.25

Full

1.0

1.0

1.0

Full

0.1

0.1

0.1

Full

3

Full

3

Full

0.1

Full

9

Full

350

Full

600/400

Full

2

3

3

3

3

0.1

0.1

9

9

350

350

300

260

2

2

Unit

MHz

MSPS

ns

ns

ns

ps rms

ns

ns

ns

Cycles

μs

ns

Cycles

1 Conversion rate is the clock rate after the CLK divider.

2 Wake-up time is dependent on the value of the decoupling capacitors.

N–1

tA

N

VIN

N+1

N+2

CLK+

CLK–

DCOA/DCOB

tCH

tCLK

tDCO

tSKEW

CH A/CH B DATA

N–9

N–8

tPD

Figure 2. CMOS Output Data Timing

N+3

N–7

N+4

N–6

N+5

N–5

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

N–1

tCH

tA

N

N+1

tCLK

N+2

N+3

N+4

N+5

tDCO

tSKEW

CH A CH B CH A CH B CH A

N–9 N–9 N–8 N–8 N–7

tPD

Figure 3. CMOS Interleaved Output Timing

CH B

N–7

CH A

N–6

CH B

N–6

CH A

N–5

Rev. 0 | Page 7 of 36

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