AD9219(RevE) Ver la hoja de datos (PDF) - Analog Devices
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AD9219 Datasheet PDF : 57 Pages
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AD9219
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
AD9219-40
AD9219-65
Temperature Min Typ Max
Min Typ Max
Unit
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Full
250
250
mV p-p
Full
1.2
1.2
V
25°C
20
20
kΩ
25°C
1.5
1.5
pF
Full
1.2
3.6
1.2
3.6
V
Full
0
0.3
0.3
V
25°C
30
30
kΩ
25°C
0.5
0.5
pF
Full
1.2
3.6
1.2
3.6
V
Full
0
0.3
0.3
V
25°C
70
70
kΩ
25°C
0.5
0.5
pF
Full
1.2
DRVDD + 0.3 1.2
DRVDD + 0.3 V
Full
0
0.3
0
0.3
V
25°C
30
30
kΩ
25°C
2
2
pF
Full
1.79
1.79
V
Full
0.05
0.05
V
LVDS
LVDS
Full
247
454
247
454
mV
Full
1.125
1.375
1.125
1.375
V
Offset binary
Offset binary
LVDS
LVDS
Full
150
250
150
250
mV
Full
1.10
1.30
1.10
1.30
V
Offset binary
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Rev. E | Page 6 of 56
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