AD8804AN Ver la hoja de datos (PDF) - Analog Devices
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AD8804AN Datasheet PDF : 16 Pages
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AD8802/AD8804
0.04
0.02
0
–0.02
x + 2σ
x
x – 2σ
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
–0.04
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150°C
Figure 13. Full-Scale Error Accelerated by Burn-In
1.0
0.5
0
–0.5
x + 2σ
x
x – 2σ
VDD = +4.5V
VREF = +4.5V
CODE = 55H
SS = 176 PCS
–1.0
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150°C
Figure 14. REF Input Resistance Accelerated by Burn-In
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 µs (13 × 12 ×
30 ns). The exact timing requirements are shown in Figure 15.
Table I. Serial-Data Word Format
ADDR
DATA
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
211 210 29 28 27 26 25 24 23 22 21 20
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and VREF inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
1
SDI
0
1
CLK
0
1
CS
0
+5V
VOUT
0V
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 15a. Timing Diagram
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
SDI 1
(DATA IN) 0
1
CLK
0
1
CS
0
+5V
VOUT
0V
AX OR DX
tCH
AX OR DX
tDS
tDH
tCS1
tCSS
tCL
tCSH
tCSW
tS
±1/2 LSB ERROR BAND
±1/2 LSB
Figure 15b. Detail Timing Diagram
RESET TIMING
1
RS
0
+5V
VOUT
2.5V
tRS
tS
±1 LSB ERROR BAND
±1 LSB
Figure 15c. Reset Timing Diagram
–6–
REV. 0
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