AD8324(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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Fabricante
AD8324 Datasheet PDF : 16 Pages
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AD8324
1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
4 Measured through a 1:1 transformer.
5 Specification is worst case over all gain codes.
6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN
Logic 1 Current (VINH = 3.3 V), TXEN
Logic 0 Current (VINL = 0 V), TXEN
Logic 1 Current (VINH = 3.3 V), SLEEP
Logic 0 Current (VINL = 0 V), SLEEP
Min
2.1
0
0
−600
50
−250
50
−250
TIMING REQUIREMENTS
Table 3. VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted
Parameter
Min
Clock Pulse Width (tWH)
16.0
Clock Period (tC)
32.0
Setup Time SDATA vs. Clock (tDS)
5.0
Setup Time DATEN vs. Clock (tES)
15.0
Hold Time SDATA vs. Clock (tDH)
5.0
Hold Time DATEN vs. Clock (tEH)
3.0
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
Typ
Max
3.3
0.8
20
−100
190
−30
190
−30
Typ
Max
10
Unit
V
V
nA
nA
µA
µA
µA
µA
Unit
ns
ns
ns
ns
ns
ns
ns
tDS
SDATA
CLK
VALID DATA WORD G1
MSB . . . LSB
tC
tVUH
VALID DATA WORD G2
DATEN
TXEN
tES
tEH
8 CLOCK CYCLES
GAIN TRANSFER (G1)
tOFF
tGS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 3. Serial Interface Timing
GAIN TRANSFER (G2)
tCN
SDATA MSB
CLK
VALID DATA BIT
MSB-1
tDS
tDH
Figure 4. SDATA Timng
MSB-2
Rev. 0 | Page 4 of 16
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