AD8324(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD8324 Datasheet PDF : 16 Pages
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AD8324
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
20 19 18 17 16
GND 1
GND 2
VIN+ 3
VIN– 4
GND 5
AD8324
TOP VIEW
(Not to Scale)
15 RAMP
14 VOUT+
13 VOUT–
12 BYP
11 NC
6 7 8 9 10
Figure 5. 20-Lead LFCSP
GND 1
20 GND
VCC 2
GND 3
19 VCC
18 TXEN
GND
VIN+
VIN–
GND
4
17 RAMP
AD8324
5 TOP VIEW 16 VOUT+
6 (Not to Scale) 15 VOUT–
7
14 BYP
DATEN 8
13 NC
SDATA 9
12 SLEEP
CLK 10
11 GND
NC = NO CONNECT
Figure 6. 20-Lead QSOP
Table 5. Pin Function Descriptions
Pin No. Pin No.
20-Lead 20-Lead
LFCSP QSOP
Mnemonic
1, 2, 5, 9, 1, 3, 4, 7,
18, 19 11, 20
GND
17, 20 2, 19
VCC
3
5
VIN+
4
6
6
8
VIN–
DATEN
7
9
8
10
10
12
12
14
13
15
14
16
15
17
16
18
SDATA
CLK
SLEEP
BYP
VOUT–
VOUT+
RAMP
TXEN
Description
Common External Ground Reference.
Common Positive External Supply Voltage.
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A
Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and
simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data
latch (holds the previous and simultaneously enables the register for serial data load).
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 µA. A
Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part.
Internal Bypass. This pin must be externally decoupled (0.1 µF capacitor).
Negative Output Signal. Must be biased to VCC. See Figure 23.
Positive Output Signal. Must be biased to VCC. See Figure 23.
External RAMP Capacitor (Optional).
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
Rev. 0 | Page 6 of 16
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