AD8045(RevB) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD8045 Datasheet PDF : 26 Pages
| |||
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12.6 V
See Figure 4
−VS − 0.7 V to +VS + 0.7 V
±VS
−VS
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
SOIC
80
30
°C/W
LFCSP
93
35
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8045. Exceeding a junction temperature of 175°C for
an extended period of time can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the AD8045 drive at the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS).
AD8045
PD = Quiescent Power + (Total Drive Power – Load Power)
( ) PD = VS × I S
+
VS
2
× VOUT
RL
–
VOUT
RL
2
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
PD
= (VS
×IS )+
(VS / 4)2
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads and exposed
paddle from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
SOIC
1.0
LFCSP
0.5
0.0
–40 –20 0
20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. B | Page 5 of 24
Share Link: 