AD7870AJN Ver la hoja de datos (PDF) - Analog Devices
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AD7870AJN Datasheet PDF : 12 Pages
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AD7870A
TIMING CHARACTERISTICS1, 2 (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V. See Figures 9 and 10.)
Parameter
Limit at TMIN, TMAX
(J Version)
Units
Conditions/Comments
t1
50
t2
0
t3
60
t4
0
t5
70
t63
57
t74
5
50
t8
0
t9
0
t10
100
t115
370
t126
135
t13
100
t14
10
100
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
CONVST Pulse Width
CS to RD Setup Time (Mode 1)
RD Pulse Width
CS to RD Hold Time (Mode 1)
RD to INT Delay
Data Access Time after RD
Bus Relinquish Time after RD
HBEN to RD Setup Time
HBEN to RD Hold Time
SSTRB to SCLK Falling Edge Setup Time
SCLK Cycle Time
SCLK to Valid Data Delay. CL = 35 pF
SCLK Rising Edge to SSTRB
Bus Relinquish Time after SCLK
NOTES
1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.
3t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
5SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6t6 SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩʈCL) and hence the time to reach 2.4 V.
Specifications subject to change without notice.
a. High-Z to VOH
b. High-Z to VOL
Figure 1. Load Circuits for Access Time
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
REV. 0
–3–
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