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AD7870AJNZ

LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC

Analog Devices 

AD7870A–SPECIFICATIONS (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, fCLK is internal, unless

otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)

Parameter

J1

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE2

Signal-to-Noise Ratio3 (SNR)

@ +25°C

TMIN to TMAX

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

Second Order Terms

Third Order Terms

Track/Hold Acquisition Time

70 dB min

70 dB min

–80 dB max

–80 dB max

–80 dB max

–80 dB max

2

µs max

VIN = 10 kHz Sine Wave, f SAMPLE = 100 kHz

Typically 71.5 dB for 0 < VIN ≤ 50 kHz

VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz

Typically –86 dB for 0 < VIN < 50 kHz

VIN = 10 kHz, fSAMPLE = 100 kHz

Typically –86 dB for 0 < VIN < 50 kHz

fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz

DC ACCURACY

Resolution

Minimum Resolution for Which

No Missing Codes Are Guaranteed

Integral Nonlinearity

Bipolar Zero Error

Positive Full-Scale Error4

Negative Full-Scale Error4

12 Bits

12 Bits

± 1/2 LSB typ

± 5 LSB max

± 5 LSB max

± 5 LSB max

ANALOG INPUT

Input Voltage Range

Input Current

± 3 Volts

± 500 µA max

REFERENCE OUTPUT

REF OUT @ +25°C

2.99 V min

3.01 V max

REF OUT Tempco

± 60 ppm/°C max

Reference Load Sensitivity (∆REF OUT/∆I) ± 1 mV max

Reference Load Current Change (0 µA–500 µA)

Reference Load Should Not Be Change During Conversion

LOGIC INPUTS

Input High Voltage, VINH

Input Low Voltage, VINL

Input Current, IIN

Input Current (12/8 CLK Input Only)

Input Capacitance, CIN5

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

DB11–DB0

Floating State Leakage Current

Floating-State Output Capacitance5

2.4 V min

0.8 V max

± 10 µA max

± 10 µA max

10 pF max

4.0 V min

0.4 V max

± 10 µA max

15 pF max

VDD = 5 V ± 5%

VDD = 5 V ± 5%

VIN = 0 V to VDD

VIN = VSS to VDD

ISOURCE = 40 µA

ISINK = 1.6 mA

CONVERSION TIME

External Clock (fCLK = 2.5 MHz)

Internal Clock

7.6/8 µs min/µs max

8/10 µs min/µs max

POWER REQUIREMENTS

VDD

VSS

IDD

ISS

Power Dissipation

+5 V

–5

13

6

95

V nom

V non

mA max

mA max

mW max

± 5% for Specified Performance

± 5% for Specified Performance

Typically 8 mA

Typically 4 mA

Typically 60 mW

NOTES

1Temperature range is as follow: J Version: 0°C to +70°C.

2VIN (pk-pk) = ± 3 V.

3SNR calculation includes distortion and noise components.

4Measured with respect to internal reference and includes bipolar offset error.

5Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. 0

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