EVAL-CED1Z Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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EVAL-CED1Z Datasheet PDF : 28 Pages
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AD7679
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
0
0
DIVSCLK[0]
Symbol 0
1
SYNC to SCLK First Edge Delay Minimum
t18
3
17
Internal SCLK Period Minimum
t19
25
60
Internal SCLK Period Maximum
t19
40
80
Internal SCLK HIGH Minimum
t20
12
22
Internal SCLK LOW Minimum
t21
7
21
SDOUT Valid Setup Time Minimum
t22
4
18
SDOUT Valid Hold Time Minimum
t23
2
4
SCLK Last Edge to SYNC Delay Minimum
t24
3
60
Busy High Width Maximum
t28
2.25
3
1
1
0
1
Unit
17
17
ns
120
240
ns
160
320
ns
50
100
ns
49
99
ns
18
18
ns
30
89
ns
140
300
ns
4.5
7.5
μs
Rev. A | Page 6 of 28
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