AD7523 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

AD7523

8-Bit, Multiplying D/A Converters

Intersil 

AD7523, AD7533

Unipolar Binary Operation - AD7533 (10-Bit DAC)

The circuit configuration for operating the AD7533 in

unipolar mode is shown in Figure 2. With positive and

negative VREF values the circuit is capable of 2-Quadrant

multiplication. The “Digital Input Code/Analog Output Value”

table for unipolar mode is given in Table 2.

TABLE 2. UNlPOLAR BINARY CODE - AD7533

DIGITAL INPUT

MSB LSB

1111111111

1000000001

(NOTE 1)

NOMINAL ANALOG OUTPUT

–VREF11----00---22----34- 

–VREF1--5--0--1-2--3--4- 

1000000000

–VREF1--5--0--1-2--2--4- 

=

–V-----R----E----F-

2

0111111111

–VREF1--5--0--1-2--1--4- 

0000000001

–VREF1----0--1-2----4- 

0000000000

–VREF1----0--0-2----4-  = 0

NOTES:

1. VOUT as shown in the Functional Diagram.

2. Nominal Full Scale for the circuit of Figure 2 is given by:

FS = –VREF11----00---22----34-  .

3. Nominal LSB magnitude for the circuit of Figure 2 is given by:

LSB = VREF1----0--1-2----4-  .

Zero Offset Adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjust trimpot of the output

operational amplifier for 0V ±1mV (Max) at VOUT.

Gain Adjustment

1. Connect all digital inputs to V+.

2. Monitor VOUT for a -VREF (1 - 1/210) reading.

3. To increase VOUT, connect a series resistor, R2, (0Ω to

250Ω) in the IOUT1 amplifier feedback loop.

4. To decrease VOUT, connect a series resistor, R1, (0Ω to

250Ω) between the reference voltage and the VREF

terminal.

Bipolar (Offset Binary) Operation - AD7523

The circuit configuration for operating the AD7523 in the

bipolar mode is given in Figure 3. Using offset binary digital

input codes and positive and negative reference voltage

values, Four-Quadrant multiplication can be realized. The

“Digital Input Code/Analog Output Value” table for bipolar

mode is given in Table 3.)

A “Logic 1” input at any digital input forces the corresponding

ladder switch to steer the bit current to IOUT1 bus. A “Logic

0” input forces the bit current to IOUT2 bus. For any code the

IOUT1 and IOUT2 bus currents are complements of one

another. The current amplifier at IOUT2 changes the polarity

of IOUT2 current and the transconductance amplifier at IOUT

output sums the two currents. This configuration doubles the

output range. The difference current resulting at zero offset

binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is

corrected by suing an external resistor, (10MΩ), from VREF

to IOUT2 (Figure 3).

TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523

DIGITAL INPUT

MSB LSB

11111111

10000001

ANALOG OUTPUT

– VR E F  11----22---78-- 

– VR E F  1----21---8-- 

10000000

0

01111111

+V R E F  1----21---8-- 

00000001

+V R E F  11----22---78-- 

00000000

+V R E F  11----22---88-- 

NOTE:

1. 1 LSB = (2–7)(VREF) = 1----12---8--(VREF) .

±10V +15V

VREF

R1

R2

MSB

15

4

14 RFEEDBACK

16

DATA

INPUTS

AD7523/ 1 IOUT1

AD7533

-

IOUT2 R4 5K

R3 5K

13 3 2

LSB

CR1

6

+

R6 10MΩ

-

CR2

6

+

VOUT

FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)

10-12

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