AD7225LR Ver la hoja de datos (PDF) - Analog Devices
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AD7225LR Datasheet PDF : 24 Pages
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AD7225
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUTB 1
24 VOUTC
VOUTA 2
23 VOUTD
VSS 3
22 VDD
VREFB 4
21 VREFC
VREFA 5 AD7225 20 VREFD
AGND
6
TOP VIEW
(Not to Scale)
19
A0
DGND 7
18 A1
LDAC 8
17 WR
DB7 9
16 DB0
DB6 10
15 DB1
DB5 11
14 DB2
DB4 12
13 DB3
Figure 2. PDIP, SOIC, CERDIP, and SSOP
VREFB 5
VREFA 6
AGND 7
NC 8
DGND 9
LDAC 10
DB7 11
4 3 2 1 28 27 26
PIN 1
INDENTFIER
AD7225
TOP VIEW
(Not to Scale)
25 VREFC
24 VREFD
23 A0
22 NC
21 A1
20 WR
19 DB0
12 13 14 15 16 17 18
NC = NO CONNECT
Figure 3. PLCC
Table 4. Pin Function Descriptions
Pin No.
PDIP, SOIC,
CERDIP, SSOP
PLCC
Mnemonic
1
2
VOUTB
2
3
VOUTA
3
4
VSS
4
5
VREFB
5
6
VREFA
6
7
AGND
7
9
DGND
8
10
LDAC
9
11
DB7
10
12
DB6
11
13
DB5
12
14
DB4
13
16
DB3
14
17
DB2
15
18
DB1
16
19
DB0
17
20
WR
18
21
A1
19
23
A0
20
24
VREFD
21
25
VREFC
22
26
VDD
23
27
VOUTD
24
28
VOUTC
N/A
1, 8, 15, 22 NC
Description
DAC Channel B Voltage Output.
DAC Channel A Voltage Output.
Negative Power Supply Connection.
Reference Voltage Connection for DAC Channel B.
Reference Voltage Connection for DAC Channel A.
Analog Ground Reference Connection.
Digital Ground Reference Connection.
Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.
Data Bit 7 (Most Significant Data Bit).
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
Data Bit 0 (Least Significant Data Bit).
Active Low Data Write Signal. Input register data is latched on the rising edge of WR.
DAC Address Select Pin.
DAC Address Select Pin.
Reference Voltage Connection for DAC Channel D.
Reference Voltage Connection for DAC Channel C.
Positive Power Supply Connection.
DAC Channel D Voltage Output.
DAC Channel C Voltage Output.
No Internal Connection.
Rev. C | Page 6 of 24
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