AD7225BQ(RevB) Ver la hoja de datos (PDF) - Analog Devices
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AD7225BQ Datasheet PDF : 12 Pages
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AD7225–SPECIFICATIONS
DUAL SUPPLY (VDD = 11.4 V to 16.5 V, VSS = –5 V ؎ 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
Parameter
K, B
Versions2
L, C
Versions2
T Version
U Version
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
8
Total Unadjusted Error
±2
Relative Accuracy
±1
Differential Nonlinearity
±1
Full-Scale Error
±1
Full-Scale Temp. Coeff.
±5
Zero Code Error @ 25°C
± 25
TMIN to TMAX
± 30
Zero Code Error Temp Coeff. ± 30
8
8
±1
±2
± 1/2
±1
±1
±1
± 1/2
±1
±5
±5
± 15
± 25
± 20
± 30
± 30
± 30
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance3
Channel-to-Channel Isolation3
AC Feedthrough3
2 to (VDD – 4)
11
100
60
–70
2 to (VDD – 4)
11
100
60
–70
2 to (VDD – 4)
11
100
60
–70
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
2.5
2.5
2.5
Voltage Output Settling Time3
Positive Full-Scale Change 5
5
5
Negative Full-Scale Change 5
5
5
Digital Feedthrough3
50
50
50
Digital Crosstalk3
50
50
50
Minimum Load Resistance
2
2
2
POWER SUPPLIES
VDD Range
IDD
ISS
11.4/16.5
10
9
11.4/16.5
10
9
SWITCHING CHARACTERISTICS3, 4
t1
@ 25°C
95
95
TMIN to TMAX
t2
@ 25°C
120
120
0
0
TMIN to TMAX
t3
@ 25°C
0
0
0
0
TMIN to TMAX
t4
@ 25°C
0
0
70
70
TMIN to TMAX
t5
@ 25°C
90
90
10
10
TMIN to TMAX
t6
@ 25°C
10
10
95
95
TMIN to TMAX
120
120
NOTES
1Maximum possible reference voltage.
2Temperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C
3Sample Tested at 25°C to ensure compliance.
4Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
11.4/16.5
12
10
95
150
0
0
0
0
70
90
10
10
95
150
8
±1
± 1/2
±1
± 1/2
±5
± 15
± 20
± 30
2 to (VDD – 4)
11
100
60
–70
2.4
0.8
±1
8
Binary
2.5
5
5
50
50
2
11.4/16.5
12
10
95
150
0
0
0
0
70
90
10
10
95
150
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C typ
mV max
mV max
µV/°C typ
VDD = +15 V ± 5%, VREF = +10 V
Guaranteed Monotonic
VDD = 14 V to 16.5 V, VREF = +10 V
V min to V max
kΩ min
pF max
dB min
dB max
Occurs when each DAC is loaded with all 1s.
VREF = 10 V p-p Sine Wave @ 10 kHz
VREF = 10 V p-p Sine Wave @ 10 kHz
V min
V max
µA max
pF max
VIN = 0 V or VDD
V/µs min
µs max
µs max
nV secs typ
nV secs typ
kΩ min
VREF = +10 V; Settling Time to ± 1/2 LSB
VREF = +10 V; Settling Time to ± 1/2 LSB
Code transition all 0s to all 1s.
Code transition all 0s to all 1s.
VOUT = +10 V
V min to V max For Specified Performance
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Write Pulse Width
Address to Write Setup Time
Address to Write Hold Time
Data Valid to Write Setup Time
Data Valid to Write Hold Time
Load DAC Pulse Width
–2–
REV. B
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