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AD711CQ

Precision, Low Cost, High Speed, BiFET Op Amp

Analog Devices 

AD711

OP AMP SETTLING TIME—

A MATHEMATICAL MODEL

The design of the AD711 gives careful attention to optimizing

individual circuit components; in addition, a careful tradeoff was

made: the gain bandwidth product (4 MHz) and slew rate

(20 V/µs) were chosen to be high enough to provide very fast

settling time but not too high to cause a significant reduction in

phase margin (and therefore stability). Thus designed, the

AD711 settles to ± 0.01%, with a 10 V output step, in under

1 µs, while retaining the ability to drive a 100 pF load capaci-

tance when operating as a unity gain follower.

If an op amp is modeled as an ideal integrator with a unity gain

crossover frequency of ωο/2π, Equation 1 will accurately de-

scribe the small signal behavior of the circuit of Figure 26a, con-

sisting of an op amp connected as an I-to-V converter at the

output of a bipolar or CMOS DAC. This equation would com-

pletely describe the output of the system if not for the op amp’s

finite slew rate and other nonlinear effects.

Equation 1.

VO

I IN

=

–R

R(C f =

ωο

CX

)

s2

+





GN

ωο

+

RC

f





s

+

1

where

ωο

2π

=op

amp’s

unity

gain

frequency

GN

=

“noise”

gain

of

circuit

1 +

R

RO 

This equation may then be solved for Cf:

Equation 2.

When RO and IO are replaced with their Thevenin VIN and RIN

equivalents, the general purpose inverting amplifier of Figure

26b is created. Note that when using this general model, capaci-

tance CX is EITHER the input capacitance of the op amp if a

simple inverting op amp is being simulated OR it is the com-

bined capacitance of the DAC output and the op amp input if

the DAC buffer is being modeled.

Figure 26b. Simplified Model of the AD711

Used as an Inverter

In either case, the capacitance CX causes the system to go from

a one-pole to a two-pole response; this additional pole increases

settling time by introducing peaking or ringing in the op amp

output. Since the value of CX can be estimated with reasonable

accuracy, Equation 2 can be used to choose a small capacitor,

CF, to cancel the input pole and optimize amplifier response.

Figure 27 is a graphical solution of Equation 2 for the AD711

with R = 4 kΩ.

Cf

=

2 − GN

Rωο

2

+

RCX ωο + (1 − GN )

Rωο

In these equations, capacitor CX is the total capacitor appearing

the inverting terminal of the op amp. When modeling a DAC

buffer application, the Norton equivalent circuit of Figure 26a

can be used directly; capacitance CX is the total capacitance of

the output of the DAC plus the input capacitance of the op amp

(since the two are in parallel).

Figure 26a. Simplified Model of the AD711 Used as a

Current-Out DAC Buffer

Figure 27. Value of Capacitor CF vs. Value of CX

The photos of Figures 28a and 28b show the dynamic response

of the AD711 in the settling test circuit of Figure 29.

The input of the settling time fixture is driven by a flat-top pulse

generator. The error signal output from the false summing node

of A1 is clamped, amplified by A2 and then clamped again. The

error signal is thus clamped twice: once to prevent overloading

amplifier A2 and then a second time to avoid overloading the

oscilloscope preamp. The Tektronix oscilloscope preamp type

7A26 was carefully chosen because it does not overload with

these input levels. Amplifier A2 needs to be a very high speed

FET-input op amp; it provides a gain of 10, amplifying the error

signal output of A1.

–8–

REV. A

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