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AD711CQ

Precision, Low Cost, High Speed, BiFET Op Amp

Analog Devices 

AD711

OPTIMIZING SETTLING TIME

Most bipolar high-speed D/A converters have current outputs;

therefore, for most applications, an external op amp is required

for current-to-voltage conversion. The settling time of the con-

verter/op amp combination depends on the settling time of the

DAC and output amplifier. A good approximation is:

tS Total = (tS DAC )2 + (tS AMP )2

The settling time of an op amp DAC buffer will vary with the

noise gain of the circuit, the DAC output capacitance, and with

the amount of external compensation capacitance across the

DAC output scaling resistor.

Settling time for a bipolar DAC is typically 100 to 500 ns. Previ-

ously, conventional op amps have required much longer settling

times than have typical state-of-the-art DACs; therefore, the

amplifier settling time has been the major limitation to a

high-speed voltage-output D-to-A function. The introduction of

the AD711/712 family of op amps with their 1 µs (to ± 0.01% of

final value) settling time now permits the full high-speed capa-

bilities of most modern DACs to be realized.

In addition to a significant improvement in settling time, the

low offset voltage, low offset voltage drift, and high open-loop

gain of the AD711 family assures 12-bit accuracy over the full

operating temperature range.

The excellent high-speed performance of the AD711 is shown in

the oscilloscope photos of Figure 25. Measurements were taken

using a low input capacitance amplifier connected directly to the

summing junction of the AD711 – both photos show the worst

case situation: a full-scale input transition. The DAC’s 4 kΩ

[10 kΩʈ8 kΩ = 4.4 kΩ] output impedance together with a 10 kΩ

feedback resistor produce an op amp noise gain of 3.25. The

current output from the DAC produces a 10 V step at the op

amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure 25b.)

Therefore, with an ideal op amp, settling to ± 1/2 LSB (± 0.01%)

requires that 375 µV or less appears at the summing junction.

This means that the error between the input and output (that

voltage which appears at the AD711 summing junction) must be

less than 375 µV. As shown in Figure 25, the total settling time

for the AD711/AD565 combination is 1.2 microseconds.

Figure 24. ±10 V Voltage Output Bipolar DAC

a. (Full-Scale Negative Transition)

b. (Full-Scale Positive Transition)

Figure 25. Settling Characteristics for AD711 with AD565A

REV. A

–7–

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