XWM8728EDS Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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Fabricante
XWM8728EDS Datasheet PDF : 28 Pages
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WM8728
MPU 2-WIRE INTERFACE TIMING
Production Data
Figure 5 Program Register Input Timing - 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCK pulse cycle time
tSCY
SCK pulse width low
tSCL
SCK pulse width high
tSCH
SDIDEM to SCK data set-up
tSSU
time for start signal
SDIDEM from SCK data hold
tSHD
time for start signal
SDIDEM to SCK data set-up
tDSU
time
SCK to SDIDEM data hold time
tDHD
SCK rise time
tSCR
SCK fall time
tSCF
SDIDEM rise time
tDR
SDIDEM fall time
tDF
SDIDEM to SCK data set-up
tESU
time for stop signal
TEST CONDITIONS
MIN
TYP
MAX
80
20
20
10
10
20
20
5
5
5
5
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.
2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.
3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire
mode.
w
PD Rev 4.2 April 2004
11
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