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AD707 Datasheet PDF : 8 Pages
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AD707
18-BIT SETTLING TIME
Figure 22 shows the AD707 settling to within 80 µV of its final
value for a 20 V output step in less than 100 µs (in the test con-
figuration shown in Figure 23). To achieve settling to 18 bits,
any amplifier specified to have a gain of 4 V/µV would appear to
be good enough, however, this is not the case. In order to truly
achieve 18-bit accuracy, the gain linearity must be better than
4 ppm.
The gain nonlinearity of the AD707 does not contribute to the
error, and the gain itself only contributes 0.1 ppm. The gain
error, along with the VOS and VOS drift errors do not comprise
1 LSB of error in an 18-bit system over the military temperature
range. If calibration is used to null offset errors, the AD707
resolves up to 20 bits at +25°C.
REFERENCE
SIGNAL
10V/Div
D.U.T.
OUTPUT
ERROR
50µV/Div
OUTPUT:
10V/Div
140 dB CMRR INSTRUMENTATION AMPLIFIER
The extremely tight dc specifications of the AD707 enable the
designer to build very high performance, high gain instrumenta-
tion amplifiers without having to select matched op amps for the
crucial first stage. For the second stage, the lowest grade AD707
is ideally suited. The CMRR is typically the same as the high
grade parts, but does not exact a premium for drift performance
(which is less critical in the second stage). Figure 24 shows an
example of the classic instrumentation amp. Figure 25 shows
that the circuit has at least 140 dB of common-mode rejection
for a ± 10 V common-mode input at a gain of 1001 (RG = 20 Ω).
–IN
RG
+IN
AD707
3
A1
6
2
10kΩ
10kΩ
AD707
2
A2
6
3
20,000
CIRCUIT GAIN = –––––– + 1
RG
R4
10kΩ
R2
10kΩ
R1
10kΩ
200Ω
AD707
2
A3
6
3
9.9kΩ
RCM R2
TIME – 50µs/Div
Figure 22. 18-Bit Settling
2x HP1N6263
200kΩ
10µF
2
OP27
3
7
4
6
VERROR x 100
10µF 0.1µF
0.1µF
–VS +VS
Figure 24. A 3 Op Amp Instrumentation Amplifier
High CMRR is obtained by first adjusting RCM until the output
does not change as the input is swept through the full common-
mode range. The value of RG, should then be selected to achieve
the desired gain. Matched resistors should be used for the
output stage so that RCM is as small as possible. The smaller the
value Of RCM, the lower the noise introduced by potentiometer
wiper vibrations. To maintain the CMRR at 140 dB over a
20°C range, the resistor ratios in the output stage, R1/R2 and
R3/R4, must track each other better than 10 ppm/°C.
INPUT
COMMON-MODE
SIGNAL: 10V/Div
CH1
FLAT-TOP
PULSE
GENERATOR
DATA
DYNAMICS
5109
OR
EQUIVALENT
2kΩ
2kΩ
VIN
2kΩ
1.9kΩ
100Ω
2
D.U.T.
AD707
3
7
4
6
10µF
10µF
0.1µF
–VS +VS
0.1µF
COMMON-MODE
ERROR REFERRED
TO INPUT: 5µV/Div
CH2
TIME – 2 sec/Div
Figure 25. Instrumentation Amplifier
Common-Mode Rejection
Figure 23. Op Amp Settling Time Test Circuit
REV. B
–7–
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